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authorDave Airlie <[email protected]>2016-11-28 00:37:25 +0000
committerDave Airlie <[email protected]>2016-12-07 23:25:18 +0000
commita5d10844eef71095cea3c1a921108c3bccc8ba01 (patch)
treeaf76af805bd9786fc96c8a45c72b109153a5c60a /src/amd/vulkan/radv_cmd_buffer.c
parentf8476769902b6c39eafb517d4412e3e52d46147b (diff)
radv: refactor descriptor set userdata emission out.
This just moves this into a separate function. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/vulkan/radv_cmd_buffer.c')
-rw-r--r--src/amd/vulkan/radv_cmd_buffer.c37
1 files changed, 22 insertions, 15 deletions
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 89eef57a958..4ac5ad78c13 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -895,6 +895,27 @@ radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer)
}
static void
+radv_emit_descriptor_set_userdata(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_descriptor_set *set,
+ unsigned idx)
+{
+ radeon_set_sh_reg_seq(cmd_buffer->cs,
+ R_00B030_SPI_SHADER_USER_DATA_PS_0 + 8 * idx, 2);
+ radeon_emit(cmd_buffer->cs, set->va);
+ radeon_emit(cmd_buffer->cs, set->va >> 32);
+
+ radeon_set_sh_reg_seq(cmd_buffer->cs,
+ R_00B130_SPI_SHADER_USER_DATA_VS_0 + 8 * idx, 2);
+ radeon_emit(cmd_buffer->cs, set->va);
+ radeon_emit(cmd_buffer->cs, set->va >> 32);
+
+ radeon_set_sh_reg_seq(cmd_buffer->cs,
+ R_00B900_COMPUTE_USER_DATA_0 + 8 * idx, 2);
+ radeon_emit(cmd_buffer->cs, set->va);
+ radeon_emit(cmd_buffer->cs, set->va >> 32);
+}
+
+static void
radv_flush_constants(struct radv_cmd_buffer *cmd_buffer,
struct radv_pipeline *pipeline,
VkShaderStageFlags stages)
@@ -1353,21 +1374,7 @@ void radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer,
if (set->descriptors[j])
ws->cs_add_buffer(cmd_buffer->cs, set->descriptors[j], 7);
- radeon_set_sh_reg_seq(cmd_buffer->cs,
- R_00B030_SPI_SHADER_USER_DATA_PS_0 + 8 * idx, 2);
- radeon_emit(cmd_buffer->cs, set->va);
- radeon_emit(cmd_buffer->cs, set->va >> 32);
-
- radeon_set_sh_reg_seq(cmd_buffer->cs,
- R_00B130_SPI_SHADER_USER_DATA_VS_0 + 8 * idx, 2);
- radeon_emit(cmd_buffer->cs, set->va);
- radeon_emit(cmd_buffer->cs, set->va >> 32);
-
- radeon_set_sh_reg_seq(cmd_buffer->cs,
- R_00B900_COMPUTE_USER_DATA_0 + 8 * idx, 2);
- radeon_emit(cmd_buffer->cs, set->va);
- radeon_emit(cmd_buffer->cs, set->va >> 32);
-
+ radv_emit_descriptor_set_userdata(cmd_buffer, set, idx);
if(set->bo)
ws->cs_add_buffer(cmd_buffer->cs, set->bo, 8);
}