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authorRob Clark <[email protected]>2020-05-16 13:32:14 -0700
committerMarge Bot <[email protected]>2020-05-19 16:06:17 +0000
commit3c355f1ae8be2a7e1f9141c5433bdbb35fdcd7e6 (patch)
tree5538e0ee102897314d7f09c09ca1ed6786cdef4f /src/amd/compiler
parentf484d63617afe67f9eb8ba98f96e5c3617aa43c8 (diff)
freedreno/ir3/validate: add checking for types and opcodes
For cases where instructions have a src and/or dst type, validate that it matches the src/dst register types. And for cases where there are different opcodes for half vs full, validate that the opcode matches. Now that we maintain this properly throughout the stages of the ir, we can drop the fixups from the RA pass. Signed-off-by: Rob Clark <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5048>
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