diff options
| author | Daniel Schürmann <[email protected]> | 2020-01-16 16:54:35 +0100 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-01-29 18:45:23 +0000 |
| commit | 71440ba0f5512fe455be66ca48b253ecc37478a9 (patch) | |
| tree | ae9619e671d1e87a3bbef4d002d7bcc75b32fee5 /src/amd/compiler/aco_ir.h | |
| parent | 8548fe19f03ecaee711ed9041be3dc05c7c22e56 (diff) | |
aco: reorder VMEM operands in ACO IR
For all VMEM instructions, the resource constant is now
in operands[0]. For MIMG instructions, the sampler shares
operands[1] with write data in case this instruction writes memory.
Moving the VADDR to be the last operand for MIMG is the first step to
support Navi NSA encoding.
Reviewed-by: Rhys Perry <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
Diffstat (limited to 'src/amd/compiler/aco_ir.h')
| -rw-r--r-- | src/amd/compiler/aco_ir.h | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/amd/compiler/aco_ir.h b/src/amd/compiler/aco_ir.h index 3f38e6aadae..1ccaf2a0158 100644 --- a/src/amd/compiler/aco_ir.h +++ b/src/amd/compiler/aco_ir.h @@ -781,8 +781,8 @@ struct DS_instruction : public Instruction { /** * Vector Memory Untyped-buffer Instructions - * Operand(0): VADDR - Address source. Can carry an index and/or offset - * Operand(1): SRSRC - Specifies which SGPR supplies T# (resource constant) + * Operand(0): SRSRC - Specifies which SGPR supplies T# (resource constant) + * Operand(1): VADDR - Address source. Can carry an index and/or offset * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant) * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data * @@ -804,8 +804,8 @@ struct MUBUF_instruction : public Instruction { /** * Vector Memory Typed-buffer Instructions - * Operand(0): VADDR - Address source. Can carry an index and/or offset - * Operand(1): SRSRC - Specifies which SGPR supplies T# (resource constant) + * Operand(0): SRSRC - Specifies which SGPR supplies T# (resource constant) + * Operand(1): VADDR - Address source. Can carry an index and/or offset * Operand(2): SOFFSET - SGPR to supply unsigned byte offset. (SGPR, M0, or inline constant) * Operand(3) / Definition(0): VDATA - Vector GPR for write result / read data * @@ -827,10 +827,11 @@ struct MTBUF_instruction : public Instruction { /** * Vector Memory Image Instructions - * Operand(0): VADDR - Address source. Can carry an offset or an index. - * Operand(1): SRSRC - Scalar GPR that specifies the resource constant. - * Operand(2): SSAMP - Scalar GPR that specifies sampler constant. - * Operand(3) / Definition(0): VDATA - Vector GPR for read / write result. + * Operand(0) SRSRC - Scalar GPR that specifies the resource constant. + * Operand(1): SSAMP - Scalar GPR that specifies sampler constant. + * or VDATA - Vector GPR for write data. + * Operand(2): VADDR - Address source. Can carry an offset or an index. + * Definition(0): VDATA - Vector GPR for read result. * */ struct MIMG_instruction : public Instruction { |