diff options
| author | Timur Kristóf <[email protected]> | 2019-10-23 21:43:50 +0200 |
|---|---|---|
| committer | Timur Kristóf <[email protected]> | 2019-10-25 10:10:42 +0200 |
| commit | d6dfce02d074d615a3b88a3fccd8ee8c7e13c010 (patch) | |
| tree | 0c4e5d7fcc55cf22019ea609817bec37a51188e6 /src/amd/compiler/README | |
| parent | e5a8616973d45909a75a708f88dfb9c3cbb5ded8 (diff) | |
aco/gfx10: Mitigate VcmpxExecWARHazard.
There is a hazard when a non-VALU instruction reads the EXEC mask
and then a VALU instruction writes the EXEC mask.
This commit adds a workaround that avoids the problem.
Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Daniel Schürmann <[email protected]>
Diffstat (limited to 'src/amd/compiler/README')
| -rw-r--r-- | src/amd/compiler/README | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/amd/compiler/README b/src/amd/compiler/README index d3ecc896bc4..79674ebe0db 100644 --- a/src/amd/compiler/README +++ b/src/amd/compiler/README @@ -181,3 +181,13 @@ Any permlane instruction that follows any VOPC instruction. Confirmed by AMD devs that despite the name, this doesn't only affect v_cmpx. Mitigated by: any VALU instruction except `v_nop`. + +### VcmpxExecWARHazard + +Triggered by: +Any non-VALU instruction reads the EXEC mask. Then, any VALU instruction writes the EXEC mask. + +Mitigated by: +A VALU instruction that writes an SGPR (or has a valid SDST operand), or `s_waitcnt_depctr 0xfffe`. +Note: `s_waitcnt_depctr` is an internal instruction, so there is no further information +about what it does or what its operand means. |