diff options
| author | Marek Olšák <[email protected]> | 2018-03-06 19:07:58 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-03-08 14:58:16 -0500 |
| commit | 75c5d25f0f34cd70246ee1b0b77a75ec82dfcecb (patch) | |
| tree | d2446c8058e5350fa3aeb222ea7bbc9ad30ea361 /src/amd/common | |
| parent | 5b68a7297d2a610faeb7353c8e49910ea1b16d43 (diff) | |
radeonsi: align command buffer starting address to fix some Raven hangs
Cc: 17.3 18.0 <[email protected]>
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 21 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
2 files changed, 21 insertions, 1 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 146098baa0c..7c13e5f70b7 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -98,7 +98,9 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, { struct amdgpu_buffer_size_alignments alignment_info = {}; struct amdgpu_heap_info vram, vram_vis, gtt; - struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}, uvd_enc = {}, vce = {}, vcn_dec = {}, vcn_enc = {}; + struct drm_amdgpu_info_hw_ip dma = {}, compute = {}, uvd = {}; + struct drm_amdgpu_info_hw_ip uvd_enc = {}, vce = {}, vcn_dec = {}; + struct drm_amdgpu_info_hw_ip vcn_enc = {}, gfx = {}; uint32_t vce_version = 0, vce_feature = 0, uvd_version = 0, uvd_feature = 0; int r, i, j; drmDevicePtr devinfo; @@ -154,6 +156,12 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, return false; } + r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_GFX, 0, &gfx); + if (r) { + fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(gfx) failed.\n"); + return false; + } + r = amdgpu_query_hw_ip_info(dev, AMDGPU_HW_IP_COMPUTE, 0, &compute); if (r) { fprintf(stderr, "amdgpu: amdgpu_query_hw_ip_info(compute) failed.\n"); @@ -340,6 +348,17 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, if (info->chip_class == SI) info->gfx_ib_pad_with_type2 = TRUE; + unsigned ib_align = 0; + ib_align = MAX2(ib_align, gfx.ib_start_alignment); + ib_align = MAX2(ib_align, compute.ib_start_alignment); + ib_align = MAX2(ib_align, dma.ib_start_alignment); + ib_align = MAX2(ib_align, uvd.ib_start_alignment); + ib_align = MAX2(ib_align, uvd_enc.ib_start_alignment); + ib_align = MAX2(ib_align, vce.ib_start_alignment); + ib_align = MAX2(ib_align, vcn_dec.ib_start_alignment); + ib_align = MAX2(ib_align, vcn_enc.ib_start_alignment); + info->ib_start_alignment = ib_align; + return true; } diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 7c86dc1cb6f..0beba9604a0 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -62,6 +62,7 @@ struct radeon_info { bool has_virtual_memory; bool gfx_ib_pad_with_type2; bool has_hw_decode; + unsigned ib_start_alignment; uint32_t num_sdma_rings; uint32_t num_compute_rings; uint32_t uvd_fw_version; |