diff options
| author | Marek Olšák <[email protected]> | 2017-07-28 21:34:02 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-08-04 02:10:04 +0200 |
| commit | 4662e45350d54d55950253d361321ba6cb291c68 (patch) | |
| tree | 9a1182ab57dcef36747a4a8cdfe3cf08753431be /src/amd/common | |
| parent | 6839d3369905eb02151334ea7b4cd39ddcfa6770 (diff) | |
ac/surface: move tile_swizzle to ac_surface and document it
Gfx9 will use it too.
Reviewed-by: Dave Airlie <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_surface.c | 5 | ||||
| -rw-r--r-- | src/amd/common/ac_surface.h | 16 |
2 files changed, 19 insertions, 2 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 26f3729adf9..4647ce46c59 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -716,7 +716,10 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, AddrBaseSwizzleIn.pTileInfo = AddrSurfInfoOut.pTileInfo; AddrBaseSwizzleIn.tileMode = AddrSurfInfoOut.tileMode; AddrComputeBaseSwizzle(addrlib, &AddrBaseSwizzleIn, &AddrBaseSwizzleOut); - surf->u.legacy.tile_swizzle = AddrBaseSwizzleOut.tileSwizzle; + + assert(AddrBaseSwizzleOut.tileSwizzle <= + u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); + surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle; } return 0; } diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 3eaef639aad..ee96003f661 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -97,7 +97,6 @@ struct legacy_surf_layout { unsigned depth_adjusted:1; unsigned stencil_adjusted:1; - uint8_t tile_swizzle; struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS]; struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS]; uint8_t tiling_index[RADEON_SURF_MAX_LEVELS]; @@ -168,6 +167,21 @@ struct radeon_surf { * they will be treated as hints (e.g. bankw, bankh) and might be * changed by the calculator. */ + + /* Tile swizzle can be OR'd with low bits of the BASE_256B address. + * The value is the same for all mipmap levels. Supported tile modes: + * - GFX6: Only macro tiling. + * - GFX9: Only *_X swizzle modes. Level 0 must not be in the mip tail. + * + * Only these surfaces are allowed to set it: + * - color (if it doesn't have to be displayable) + * - DCC (same tile swizzle as color) + * - FMASK + * - CMASK if it's TC-compatible or if the gen is GFX9 + * - depth/stencil if HTILE is not TC-compatible and if the gen is not GFX9 + */ + uint8_t tile_swizzle; + uint64_t surf_size; uint64_t dcc_size; uint64_t htile_size; |