diff options
| author | Marek Olšák <[email protected]> | 2019-09-12 19:00:23 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-09-18 14:39:06 -0400 |
| commit | 2c62b461e99c0d1d40d5aa16acfdd3df2fb790cd (patch) | |
| tree | cdece3ca5321b81e5f1f116d3e22266b17b4ce17 /src/amd/common | |
| parent | 05da025f350cb83e1125d6a931ccf9a87223bb69 (diff) | |
ac: move PBB MAX_ALLOC_COUNT into radeon_info
Reviewed-by: Timothy Arceri <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 32 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
2 files changed, 33 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 5fb1e26376a..aa09ba815ef 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -538,6 +538,38 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->has_gds_ordered_append = info->chip_class >= GFX7 && info->drm_minor >= 29; + + if (info->chip_class >= GFX9) { + unsigned pc_lines = 0; + + switch (info->family) { + case CHIP_VEGA10: + case CHIP_VEGA12: + case CHIP_VEGA20: + pc_lines = 2048; + break; + case CHIP_RAVEN: + case CHIP_RAVEN2: + case CHIP_RENOIR: + case CHIP_NAVI10: + case CHIP_NAVI12: + pc_lines = 1024; + break; + case CHIP_NAVI14: + pc_lines = 512; + break; + default: + assert(0); + } + + if (info->chip_class >= GFX10) { + info->pbb_max_alloc_count = pc_lines / 3; + } else { + info->pbb_max_alloc_count = + MIN2(128, pc_lines / (4 * info->max_se)); + } + } + return true; } diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 9986d58202a..555f7175e87 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -66,6 +66,7 @@ struct radeon_info { bool has_load_ctx_reg_pkt; bool has_out_of_order_rast; bool cpdma_prefetch_writes_memory; + uint32_t pbb_max_alloc_count; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ |