diff options
| author | Samuel Pitoiset <[email protected]> | 2019-08-21 11:32:25 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-27 08:04:41 +0200 |
| commit | 021feb1bf61b06f813d41eb34831e620c9bc91bf (patch) | |
| tree | 3f6cd60415f44c4c8babc29b80a687874e4fb0fa /src/amd/common | |
| parent | 20c5db02b570b946e6f029a0b5112df5376d010f (diff) | |
ac: add rbplus_allowed to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 10 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
2 files changed, 11 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 3f3a236ba80..49ad93407ec 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -457,6 +457,16 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->has_rbplus = info->family == CHIP_STONEY || info->chip_class >= GFX9; + /* Some chips have RB+ registers, but don't support RB+. Those must + * always disable it. + */ + info->rbplus_allowed = info->has_rbplus && + (info->family == CHIP_STONEY || + info->family == CHIP_VEGA12 || + info->family == CHIP_RAVEN || + info->family == CHIP_RAVEN2 || + info->family == CHIP_RENOIR); + info->has_out_of_order_rast = info->chip_class >= GFX8 && info->max_se >= 2; diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 0f802216bdc..f676600e5b9 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -62,6 +62,7 @@ struct radeon_info { bool has_distributed_tess; bool has_dcc_constant_encode; bool has_rbplus; /* if RB+ registers exist */ + bool rbplus_allowed; /* if RB+ is allowed */ bool has_load_ctx_reg_pkt; bool has_out_of_order_rast; bool cpdma_prefetch_writes_memory; |