diff options
| author | Marek Olšák <[email protected]> | 2018-05-02 18:53:24 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-05-10 18:39:57 -0400 |
| commit | e720cb61354167e5ff75202affe86185a18386ba (patch) | |
| tree | 69b39bffd38ffa7215915786c4e8831147336e95 /src/amd/common | |
| parent | 3060f62340b2f232907db0c48b6c6c6eba3d1752 (diff) | |
radeonsi: clean up the reset status query implementation
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 4 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 68750b2db28..7678a18b355 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -320,6 +320,8 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->htile_cmask_support_1d_tiling = true; info->si_TA_CS_BC_BASE_ADDR_allowed = true; info->has_bo_metadata = true; + info->has_gpu_reset_status_query = true; + info->has_gpu_reset_counter_query = false; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ @@ -471,6 +473,8 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling); printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed); printf(" has_bo_metadata = %u\n", info->has_bo_metadata); + printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query); + printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 340c368bda3..f5b74579ef1 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -100,6 +100,8 @@ struct radeon_info { bool htile_cmask_support_1d_tiling; bool si_TA_CS_BC_BASE_ADDR_allowed; bool has_bo_metadata; + bool has_gpu_reset_status_query; + bool has_gpu_reset_counter_query; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ |