diff options
| author | Marek Olšák <[email protected]> | 2018-05-01 14:34:19 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-05-24 13:41:56 -0400 |
| commit | 8c1c451a9088a8a62cac447bcbadd049ee428079 (patch) | |
| tree | fa4248d012e630817752f8d87ac85b42ef872e55 /src/amd/common | |
| parent | 473af0b541b2583f4c72ffe885cff5ec2660a45f (diff) | |
ac/surface/gfx6: don't overallocate mipmapped HTILE
Tested-by: Dieter Nützel <[email protected]>
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_surface.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index b50157cdb9a..6600ff6b7ef 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -934,8 +934,17 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, /* Make sure HTILE covers the whole miptree, because the shader reads * TC-compatible HTILE even for levels where it's disabled by DB. */ - if (surf->htile_size && config->info.levels > 1) - surf->htile_size *= 2; + if (surf->htile_size && config->info.levels > 1 && + surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) { + /* MSAA can't occur with levels > 1, so ignore the sample count. */ + const unsigned total_pixels = surf->surf_size / surf->bpe; + const unsigned htile_block_size = 8 * 8; + const unsigned htile_element_size = 4; + + surf->htile_size = (total_pixels / htile_block_size) * + htile_element_size; + surf->htile_size = align(surf->htile_size, surf->htile_alignment); + } surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED; surf->is_displayable = surf->is_linear || |