diff options
| author | Samuel Pitoiset <[email protected]> | 2018-01-04 16:24:22 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-01-05 09:49:45 +0100 |
| commit | 50cfad0298bbb4e341664ed0ec8b4d9b429988dc (patch) | |
| tree | e89d8341e1382d11ac7f9bd43961bd08c8a4418b /src/amd/common | |
| parent | 85769759bf1f3297af36eb9aed67d9de418ca12a (diff) | |
amd/common: use ac_image_load when lod is zero
This might decrease VGPR spilling, because we no longer
have to use v4i32 for 2D fetches when level == 0. We now
use v2i32 for those cases.
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_nir_to_llvm.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index e9f997c7a45..90faf0537f7 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -2252,7 +2252,9 @@ static LLVMValueRef build_tex_intrinsic(struct ac_nir_context *ctx, case nir_texop_txf: case nir_texop_txf_ms: case nir_texop_samples_identical: - args->opcode = instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? ac_image_load : ac_image_load_mip; + args->opcode = lod_is_zero || + instr->sampler_dim == GLSL_SAMPLER_DIM_MS ? + ac_image_load : ac_image_load_mip; args->compare = false; args->offset = false; break; |