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authorSamuel Pitoiset <[email protected]>2017-12-18 22:06:38 +0100
committerSamuel Pitoiset <[email protected]>2017-12-19 21:26:25 +0100
commit4237c3d64570fb1fd295473f3fa9e45a83946a81 (patch)
tree4582a684948305ee7bbb751dfa48c320dfe568d9 /src/amd/common
parent0c4a30eb51d0affe85ff9bd80b733ca5285221e1 (diff)
radv: properly load unused gl_LocalInvocationID/gl_WorkGroupID components
F1 2017 looks good now. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/common')
-rw-r--r--src/amd/common/ac_nir_to_llvm.c21
1 files changed, 18 insertions, 3 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index bd5748d80d5..cbc6d1b61b1 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -94,7 +94,7 @@ struct nir_to_llvm_context {
LLVMValueRef push_constants;
LLVMValueRef view_index;
LLVMValueRef num_work_groups;
- LLVMValueRef workgroup_ids;
+ LLVMValueRef workgroup_ids[3];
LLVMValueRef local_invocation_ids;
LLVMValueRef tg_size;
@@ -751,7 +751,15 @@ static void create_function(struct nir_to_llvm_context *ctx,
add_user_sgpr_argument(&args, ctx->ac.v3i32,
&ctx->num_work_groups);
}
- add_sgpr_argument(&args, ctx->ac.v3i32, &ctx->workgroup_ids);
+
+ for (int i = 0; i < 3; i++) {
+ ctx->workgroup_ids[i] = NULL;
+ if (ctx->shader_info->info.cs.uses_block_id[i]) {
+ add_sgpr_argument(&args, ctx->ac.i32,
+ &ctx->workgroup_ids[i]);
+ }
+ }
+
if (ctx->shader_info->info.cs.uses_local_invocation_idx)
add_sgpr_argument(&args, ctx->ac.i32, &ctx->tg_size);
add_vgpr_argument(&args, ctx->ac.v3i32, &ctx->local_invocation_ids);
@@ -4050,7 +4058,14 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
switch (instr->intrinsic) {
case nir_intrinsic_load_work_group_id: {
- result = ctx->nctx->workgroup_ids;
+ LLVMValueRef values[3];
+
+ for (int i = 0; i < 3; i++) {
+ values[i] = ctx->nctx->workgroup_ids[i] ?
+ ctx->nctx->workgroup_ids[i] : ctx->ac.i32_0;
+ }
+
+ result = ac_build_gather_values(&ctx->ac, values, 3);
break;
}
case nir_intrinsic_load_base_vertex: {