diff options
| author | Samuel Pitoiset <[email protected]> | 2019-08-02 12:10:43 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-27 08:04:05 +0200 |
| commit | d62d2840c42d0eb3433c6c0c8bfe8d506c0475b9 (patch) | |
| tree | 15dc1af10891dce96f59d2881de6c3e1999a8cdd /src/amd/common | |
| parent | af65f9431e0fea5df0957987efeb0b87cee6cadc (diff) | |
ac: add has_clear_state to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 6 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index b02f1471463..ed6e273c598 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -441,6 +441,12 @@ bool ac_query_gpu_info(int fd, void *dev_p, info->num_sdma_rings = util_bitcount(dma.available_rings); info->num_compute_rings = util_bitcount(compute.available_rings); + /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs + * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc. + * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel. + */ + info->has_clear_state = info->chip_class >= GFX7; + /* Get the number of good compute units. */ info->num_good_compute_units = 0; for (i = 0; i < info->max_se; i++) diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 8418a62e387..69bac7252bf 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -58,6 +58,7 @@ struct radeon_info { uint32_t num_sdma_rings; uint32_t clock_crystal_freq; uint32_t tcc_cache_line_size; + bool has_clear_state; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ |