diff options
| author | Marek Olšák <[email protected]> | 2018-05-02 19:54:35 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2018-05-10 18:40:10 -0400 |
| commit | 9b1fdfc541ed0eb62632e893b2142500bb003453 (patch) | |
| tree | b6ebd09c3b782f8153d29fe312e585409feb35e2 /src/amd/common | |
| parent | d26696283d494822f2df72a6b94d51e70f91c4d9 (diff) | |
ac/gpu_info: add has_2d_tiling
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 2 | ||||
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 7e40ffcf3e7..906e76ba051 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -337,6 +337,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->has_sparse_vm_mappings = info->chip_class >= CIK && info->chip_class <= VI && info->drm_minor >= 13; + info->has_2d_tiling = true; info->num_render_backends = amdinfo->rb_pipes; /* The value returned by the kernel driver was wrong. */ @@ -496,6 +497,7 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch); printf(" has_unaligned_shader_loads = %u\n", info->has_unaligned_shader_loads); printf(" has_sparse_vm_mappings = %u\n", info->has_sparse_vm_mappings); + printf(" has_2d_tiling = %u\n", info->has_2d_tiling); printf("Shader core info:\n"); printf(" max_shader_clock = %i\n", info->max_shader_clock); diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 7caa6543695..fb44f7c8af4 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -108,6 +108,7 @@ struct radeon_info { bool has_indirect_compute_dispatch; bool has_unaligned_shader_loads; bool has_sparse_vm_mappings; + bool has_2d_tiling; /* Shader cores. */ uint32_t r600_max_quad_pipes; /* wave size / 16 */ |