diff options
| author | Samuel Pitoiset <[email protected]> | 2018-03-08 17:30:05 +0100 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2018-03-09 09:28:20 +0100 |
| commit | 365850fd68452f12c91d39568f8179263903bb6f (patch) | |
| tree | 11dd1ca4d734314978effc9265d1197c150aef62 /src/amd/common | |
| parent | 68201ab2dae3fc8550e013ace110b77c2d1b94a9 (diff) | |
ac/nir: set number of channels for packed mrt exports
Bit 0 enables VSRC0 (R in low bits, G high) and bit 2 enables
VSRC1 (B in low bits, A high).
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/common')
| -rw-r--r-- | src/amd/common/ac_nir_to_llvm.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 9b850698608..b8cfdc3c1a4 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -5910,22 +5910,27 @@ si_llvm_init_export_args(struct radv_shader_context *ctx, break; case V_028714_SPI_SHADER_FP16_ABGR: + args->enabled_channels = 0x5; packf = ac_build_cvt_pkrtz_f16; break; case V_028714_SPI_SHADER_UNORM16_ABGR: + args->enabled_channels = 0x5; packf = ac_build_cvt_pknorm_u16; break; case V_028714_SPI_SHADER_SNORM16_ABGR: + args->enabled_channels = 0x5; packf = ac_build_cvt_pknorm_i16; break; case V_028714_SPI_SHADER_UINT16_ABGR: + args->enabled_channels = 0x5; packi = ac_build_cvt_pk_u16; break; case V_028714_SPI_SHADER_SINT16_ABGR: + args->enabled_channels = 0x5; packi = ac_build_cvt_pk_i16; break; |