Revert "ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set"

This reverts commit f6d87ec8a908250af5e805c8042524ac360094a2.

It breaks RADV.

Fixes: f6d87ec8a908250af5e805c8042524ac360094a2 "ac/surface: remove RADEON_SURF_TC_COMPATIBLE_HTILE and assume it's always set"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4864>

2 files changed, 10 insertions, 13 deletions

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index ef266922564..474be97d0b4 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -651,8 +651,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	AddrSurfInfoIn.flags.cube = config->is_cube;
 	AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
 	AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
-	AddrSurfInfoIn.flags.tcCompatible = info->chip_class >= GFX8 &&
-					    AddrSurfInfoIn.flags.depth;
+	AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 
 	/* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
 	 * requested, because TC-compatible HTILE requires 2D tiling.
@@ -773,7 +772,6 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	surf->htile_size = 0;
 	surf->htile_slice_size = 0;
 	surf->htile_alignment = 1;
-	surf->tc_compatible_htile_allowed = AddrSurfInfoIn.flags.tcCompatible;
 
 	const bool only_stencil = (surf->flags & RADEON_SURF_SBUFFER) &&
 				  !(surf->flags & RADEON_SURF_ZBUFFER);
@@ -790,11 +788,10 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 			if (level > 0)
 				continue;
 
-			if (!AddrSurfInfoOut.tcCompatible)
+			if (!AddrSurfInfoOut.tcCompatible) {
 				AddrSurfInfoIn.flags.tcCompatible = 0;
-
-			if (!AddrSurfInfoOut.tcCompatible || !surf->htile_size)
-				surf->tc_compatible_htile_allowed = false;
+				surf->flags &= ~RADEON_SURF_TC_COMPATIBLE_HTILE;
+			}
 
 			if (AddrSurfInfoIn.flags.matchStencilTileCfg) {
 				AddrSurfInfoIn.flags.matchStencilTileCfg = 0;
@@ -940,7 +937,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 	 * TC-compatible HTILE even for levels where it's disabled by DB.
 	 */
 	if (surf->htile_size && config->info.levels > 1 &&
-	    surf->tc_compatible_htile_allowed) {
+	    surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) {
 		/* MSAA can't occur with levels > 1, so ignore the sample count. */
 		const unsigned total_pixels = surf->surf_size / surf->bpe;
 		const unsigned htile_block_size = 8 * 8;
@@ -1572,12 +1569,14 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 		AddrSurfInfoIn.bpp = surf->bpe * 8;
 	}
 
-	AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
+	bool is_color_surface = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
+	AddrSurfInfoIn.flags.color = is_color_surface &&
 	                             !(surf->flags & RADEON_SURF_NO_RENDER_TARGET);
 	AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
 	AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
 	/* flags.texture currently refers to TC-compatible HTILE */
-	AddrSurfInfoIn.flags.texture = 1;
+	AddrSurfInfoIn.flags.texture = is_color_surface ||
+				       surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
 	AddrSurfInfoIn.flags.opt4space = 1;
 
 	AddrSurfInfoIn.numMipLevels = config->info.levels;
@@ -1717,7 +1716,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 	}
 
 	surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
-	surf->tc_compatible_htile_allowed = surf->htile_size != 0;
 
 	/* Query whether the surface is displayable. */
 	/* This is only useful for surfaces that are allocated without SCANOUT. */
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index bd90d958ea2..8fbf7488c4a 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -67,7 +67,7 @@ enum radeon_micro_mode {
 /* bits 19 and 20 are reserved for libdrm_radeon, don't use them */
 #define RADEON_SURF_FMASK                       (1 << 21)
 #define RADEON_SURF_DISABLE_DCC                 (1 << 22)
-/* gap */
+#define RADEON_SURF_TC_COMPATIBLE_HTILE         (1 << 23)
 #define RADEON_SURF_IMPORTED                    (1 << 24)
 /* gap */
 #define RADEON_SURF_SHAREABLE                   (1 << 26)
@@ -198,7 +198,6 @@ struct radeon_surf {
     unsigned                    has_stencil:1;
     /* This might be true even if micro_tile_mode isn't displayable or rotated. */
     unsigned                    is_displayable:1;
-    unsigned                    tc_compatible_htile_allowed:1;
     /* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
     unsigned                    micro_tile_mode:3;
     uint32_t                    flags;