diff options
| author | Marek Olšák <[email protected]> | 2019-05-14 22:16:20 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-05-15 20:54:10 -0400 |
| commit | ccfcb9d818b40564001b3cf2516367526de26c1d (patch) | |
| tree | 635e075d82a6793001a8982866684e36be61d4d8 /src/amd/common/ac_surface.c | |
| parent | e5cc363f43ba3e4b0800dc1e4fae1395f65a1275 (diff) | |
ac: rename SI-CIK-VI to GFX6-GFX7-GFX8
Acked-by: Dave Airlie <[email protected]>
We already use GFX9 and I don't want us to have confusing naming
in the driver. GFXn naming is better from the driver perspective,
because it's the real version of the gfx portion of the hw. Also,
CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI.
It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have
nothing to do with GFXn and they have their own version numbers.
Diffstat (limited to 'src/amd/common/ac_surface.c')
| -rw-r--r-- | src/amd/common/ac_surface.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index f9dd4f5d77d..a9433b9696c 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -452,7 +452,7 @@ static void gfx6_set_micro_tile_mode(struct radeon_surf *surf, { uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]]; - if (info->chip_class >= CIK) + if (info->chip_class >= GFX7) surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode); else surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode); @@ -526,8 +526,8 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib, } /* Compute tile swizzle. */ - /* TODO: fix tile swizzle with mipmapping for SI */ - if ((info->chip_class >= CIK || config->info.levels == 1) && + /* TODO: fix tile swizzle with mipmapping for GFX6 */ + if ((info->chip_class >= GFX7 || config->info.levels == 1) && config->info.surf_index && surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D && !(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) && @@ -567,7 +567,7 @@ void ac_compute_cmask(const struct radeon_info *info, if (surf->flags & RADEON_SURF_Z_OR_SBUFFER) return; - assert(info->chip_class <= VI); + assert(info->chip_class <= GFX8); switch (num_pipes) { case 2: @@ -732,7 +732,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, * driver team). */ AddrSurfInfoIn.flags.dccCompatible = - info->chip_class >= VI && + info->chip_class >= GFX8 && !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) && !(surf->flags & RADEON_SURF_DISABLE_DCC) && !compressed && @@ -742,7 +742,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0; AddrSurfInfoIn.flags.compressZ = !!(surf->flags & RADEON_SURF_Z_OR_SBUFFER); - /* On CI/VI, the DB uses the same pitch and tile mode (except tilesplit) + /* On GFX7-GFX8, the DB uses the same pitch and tile mode (except tilesplit) * for Z and stencil. This can cause a number of problems which we work * around here: * @@ -799,7 +799,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER)); assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1); - if (info->chip_class == SI) { + if (info->chip_class == GFX6) { if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) { if (surf->bpe == 2) AddrSurfInfoIn.tileIndex = 11; /* 16bpp */ @@ -816,7 +816,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib, AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */ } } else { - /* CIK - VI */ + /* GFX7 - GFX8 */ if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */ else |