diff options
| author | Marek Olšák <[email protected]> | 2020-06-11 04:30:04 -0400 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-06-11 10:01:57 +0000 |
| commit | 56f2a77a4149e637d8524780bed121979e7d134e (patch) | |
| tree | 866f35ac95c03257da1d76800f55a2ab18eafabb /src/amd/common/ac_surface.c | |
| parent | 7406ea37e6b666d474ab62982ca333d518c84231 (diff) | |
ac/surface: enable DCC for the first level in the mip tail on gfx10
Acked-by: Pierre-Eric Pelloux-Prayer <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5424>
Diffstat (limited to 'src/amd/common/ac_surface.c')
| -rw-r--r-- | src/amd/common/ac_surface.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index be55e6deaaa..206cdd26dbe 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -1481,7 +1481,16 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, */ for (unsigned i = 0; i < in->numMipLevels; i++) { if (meta_mip_info[i].inMiptail) { - surf->num_dcc_levels = i; + /* GFX10 can only compress the first level + * in the mip tail. + * + * TODO: Try to do the same thing for gfx9 + * if there are no regressions. + */ + if (info->chip_class >= GFX10) + surf->num_dcc_levels = i + 1; + else + surf->num_dcc_levels = i; break; } } |