ac/nir: Add workaround for GFX9 buffer views.

On GFX9 whether the buffer size is interpreted as elements or bytes
depends on whether IDXEN is enabled in the instruction. If the index
is a constant zero, LLVM optimizes IDXEN to 0.

Now the size in elements is interpreted in bytes which of course
results in out of bounds accesses.

The correct fix is most likely to disable the LLVM optimization,
but we need something to work with LLVM <= 6.0.

radeonsi does the max between stride and element count on the CPU
but that results in the size intrinsics returning the wrong size
for the buffer. This would cause CTS errors for radv.

v2: Also include the store changes.

Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Samuel Pitoiset <[email protected]>

1 files changed, 4 insertions, 0 deletions

diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 2f222cf8d61..6b9a91c92a9 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -188,6 +188,10 @@ struct ac_shader_abi {
 	/* Whether to clamp the shadow reference value to [0,1]on VI. Radeonsi currently
 	 * uses it due to promoting D16 to D32, but radv needs it off. */
 	bool clamp_shadow_reference;
+
+	/* Whether to workaround GFX9 ignoring the stride for the buffer size if IDXEN=0
+	* and LLVM optimizes an indexed load with constant index to IDXEN=0. */
+	bool gfx9_stride_size_workaround;
 };
 
 #endif /* AC_SHADER_ABI_H */