diff options
| author | Dave Airlie <[email protected]> | 2017-02-16 03:42:56 +0000 |
|---|---|---|
| committer | Dave Airlie <[email protected]> | 2017-02-16 22:57:15 +0000 |
| commit | cae1ff1a4b1f696fc6c2496d281c2548a097e753 (patch) | |
| tree | 1caddae6ee3494c53476f20f9930f29d23a6e252 /src/amd/common/ac_llvm_build.c | |
| parent | 40bf7ba023a3a9b2027aa0b51adb6a591e472d59 (diff) | |
radeon/ac: add ac_emit_imsb helper.
We want to use a different intrinsic on newer llvm, so move this
code to a shared area.
Reviewed-by: Edward O'Callaghan <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/amd/common/ac_llvm_build.c')
| -rw-r--r-- | src/amd/common/ac_llvm_build.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c index 20216a74947..180fd2414a5 100644 --- a/src/amd/common/ac_llvm_build.c +++ b/src/amd/common/ac_llvm_build.c @@ -763,3 +763,27 @@ ac_emit_sendmsg(struct ac_llvm_context *ctx, ac_emit_llvm_intrinsic(ctx, intr_name, ctx->voidt, args, 2, 0); } + +LLVMValueRef +ac_emit_imsb(struct ac_llvm_context *ctx, + LLVMValueRef arg, + LLVMTypeRef dst_type) +{ + LLVMValueRef msb = ac_emit_llvm_intrinsic(ctx, "llvm.AMDGPU.flbit.i32", + dst_type, &arg, 1, + AC_FUNC_ATTR_READNONE); + + /* The HW returns the last bit index from MSB, but NIR/TGSI wants + * the index from LSB. Invert it by doing "31 - msb". */ + msb = LLVMBuildSub(ctx->builder, LLVMConstInt(ctx->i32, 31, false), + msb, ""); + + LLVMValueRef all_ones = LLVMConstInt(ctx->i32, -1, true); + LLVMValueRef cond = LLVMBuildOr(ctx->builder, + LLVMBuildICmp(ctx->builder, LLVMIntEQ, + arg, LLVMConstInt(ctx->i32, 0, 0), ""), + LLVMBuildICmp(ctx->builder, LLVMIntEQ, + arg, all_ones, ""), ""); + + return LLVMBuildSelect(ctx->builder, cond, all_ones, msb, ""); +} |