diff options
| author | Samuel Pitoiset <[email protected]> | 2019-08-20 17:16:41 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-27 08:04:26 +0200 |
| commit | b027ad66d729e31430d63406e70ac52d373e8fec (patch) | |
| tree | 335b730cdef438c528885c660442e178538db813 /src/amd/common/ac_gpu_info.h | |
| parent | ed720af46d5954a4c10d16574791d3c7ced19a21 (diff) | |
ac: add has_out_of_order_rast to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/amd/common/ac_gpu_info.h')
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 10a3205f44d..ea6b9111108 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -63,6 +63,7 @@ struct radeon_info { bool has_dcc_constant_encode; bool has_rbplus; /* if RB+ registers exist */ bool has_load_ctx_reg_pkt; + bool has_out_of_order_rast; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ |