diff options
| author | Marek Olšák <[email protected]> | 2019-01-04 19:19:54 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-04-04 09:53:24 -0400 |
| commit | 2c09eb41221eb704e9e7a21654828173158d1a7d (patch) | |
| tree | 6adb48d0372e6dd5562080ef7740190414abb9a6 /src/amd/common/ac_gpu_info.h | |
| parent | 029bfa3d253ca70186e245ccf0a7e17bb40a5bab (diff) | |
radeonsi: add support for displayable DCC for 1 RB chips
This is the simpler codepath - just disable RB and pipe alignment for DCC.
Diffstat (limited to 'src/amd/common/ac_gpu_info.h')
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index b1ef9c53734..99fed520618 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -56,6 +56,9 @@ struct radeon_info { uint32_t clock_crystal_freq; uint32_t tcc_cache_line_size; + /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ + bool use_display_dcc_unaligned; + /* Memory info. */ uint32_t pte_fragment_size; uint32_t gart_page_size; |