diff options
| author | Marek Olšák <[email protected]> | 2019-01-04 19:39:01 -0500 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-04-04 09:53:24 -0400 |
| commit | 1f21396431a03dc4e5a542628d7d8370973c967f (patch) | |
| tree | 70cdc799793f64a8ee03987e9c93c1b099f30e8c /src/amd/common/ac_gpu_info.h | |
| parent | 2c09eb41221eb704e9e7a21654828173158d1a7d (diff) | |
radeonsi: add support for displayable DCC for multi-RB chips
A compute shader is used to reorder DCC data from aligned to unaligned.
Diffstat (limited to 'src/amd/common/ac_gpu_info.h')
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index 99fed520618..5241c28f2a7 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -56,8 +56,11 @@ struct radeon_info { uint32_t clock_crystal_freq; uint32_t tcc_cache_line_size; + /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ bool use_display_dcc_unaligned; + /* Allocate both aligned and unaligned DCC and use the retile blit. */ + bool use_display_dcc_with_retile_blit; /* Memory info. */ uint32_t pte_fragment_size; |