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| author | Samuel Pitoiset <[email protected]> | 2019-08-20 17:20:42 +0200 |
|---|---|---|
| committer | Samuel Pitoiset <[email protected]> | 2019-08-27 08:04:29 +0200 |
| commit | 2b9c371575a83437f4150ee83843fab3271d3978 (patch) | |
| tree | f43fe89f7af6aa23a83a32e58341ff6f86867029 /src/amd/common/ac_gpu_info.h | |
| parent | b027ad66d729e31430d63406e70ac52d373e8fec (diff) | |
ac: add cpdma_prefetch_writes_memory to ac_gpu_info
Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Diffstat (limited to 'src/amd/common/ac_gpu_info.h')
| -rw-r--r-- | src/amd/common/ac_gpu_info.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h index ea6b9111108..a1d4d142493 100644 --- a/src/amd/common/ac_gpu_info.h +++ b/src/amd/common/ac_gpu_info.h @@ -64,6 +64,7 @@ struct radeon_info { bool has_rbplus; /* if RB+ registers exist */ bool has_load_ctx_reg_pkt; bool has_out_of_order_rast; + bool cpdma_prefetch_writes_memory; /* There are 2 display DCC codepaths, because display expects unaligned DCC. */ /* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */ |