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authorMarek Olšák <[email protected]>2018-05-02 19:28:44 -0400
committerMarek Olšák <[email protected]>2018-05-10 18:40:03 -0400
commite9c08bc658543d3bc5f3907f571920ae5c736e12 (patch)
tree71e64922efb0400100d7ca72cd2ad8f3a4aa03ad /src/amd/common/ac_gpu_info.c
parent64265ac8d53367c143050df9a8b08b224185e9ae (diff)
ac/gpu_info: add has_indirect_compute_dispatch
Reviewed-by: Nicolai Hähnle <[email protected]>
Diffstat (limited to 'src/amd/common/ac_gpu_info.c')
-rw-r--r--src/amd/common/ac_gpu_info.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index 4eeb6042eef..5a395772460 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -327,6 +327,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
/* DRM 3.1.0 doesn't flush TC for VI correctly. */
info->kernel_flushes_tc_l2_after_ib = info->chip_class != VI ||
info->drm_minor >= 2;
+ info->has_indirect_compute_dispatch = true;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
@@ -483,6 +484,7 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
+ printf(" has_indirect_compute_dispatch = %u\n", info->has_indirect_compute_dispatch);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);