diff options
| author | Marek Olšák <[email protected]> | 2019-05-08 20:49:58 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2019-05-16 13:15:36 -0400 |
| commit | 894e017c9c88a678c8cacd4b51658459c941bc0a (patch) | |
| tree | 8d96de7bd2c0fc5bb61c0ac6755914f9c704672a /src/amd/common/ac_gpu_info.c | |
| parent | 4549c3678865236216952f649fa5ed0115fe81b9 (diff) | |
r600+radeonsi: use ctx_query_reset_status on radeon
This allows a nice cleanup, because the winsys always handles it.
Diffstat (limited to 'src/amd/common/ac_gpu_info.c')
| -rw-r--r-- | src/amd/common/ac_gpu_info.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c index 2e8f943d204..7c8ca9cf48d 100644 --- a/src/amd/common/ac_gpu_info.c +++ b/src/amd/common/ac_gpu_info.c @@ -379,7 +379,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev, info->si_TA_CS_BC_BASE_ADDR_allowed = true; info->has_bo_metadata = true; info->has_gpu_reset_status_query = true; - info->has_gpu_reset_counter_query = false; info->has_eqaa_surface_allocator = true; info->has_format_bc1_through_bc7 = true; /* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */ @@ -568,7 +567,6 @@ void ac_print_gpu_info(struct radeon_info *info) printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed); printf(" has_bo_metadata = %u\n", info->has_bo_metadata); printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query); - printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query); printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator); printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7); printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib); |