amdgpu/addrlib: Cleanup.

Signed-off-by: Nicolai Hähnle <[email protected]>

4 files changed, 30 insertions, 29 deletions

diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 839a26833a6..3c0607ef266 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -861,7 +861,7 @@ VOID CiLib::HwlFmaskPostThunkSurfInfo(
 AddrTileMode CiLib::HwlDegradeThickTileMode(
     AddrTileMode        baseTileMode,   ///< [in] base tile mode
     UINT_32             numSlices,      ///< [in] current number of slices
-    UINT_32*            pBytesPerTile   ///< [in/out] pointer to bytes per slice
+    UINT_32*            pBytesPerTile   ///< [in,out] pointer to bytes per slice
     ) const
 {
     return baseTileMode;
@@ -880,7 +880,7 @@ AddrTileMode CiLib::HwlDegradeThickTileMode(
 ****************************************************************************************************
 */
 VOID CiLib::HwlOverrideTileMode(
-    ADDR_COMPUTE_SURFACE_INFO_INPUT*    pInOut      ///< [in/out] input output structure
+    ADDR_COMPUTE_SURFACE_INFO_INPUT*    pInOut      ///< [in,out] input output structure
     ) const
 {
     AddrTileMode tileMode = pInOut->tileMode;
@@ -1041,7 +1041,7 @@ VOID CiLib::HwlOverrideTileMode(
 ****************************************************************************************************
 */
 VOID CiLib::HwlSelectTileMode(
-    ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut     ///< [in/out] input output structure
+    ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut     ///< [in,out] input output structure
     ) const
 {
     AddrTileMode tileMode;
@@ -1956,14 +1956,14 @@ VOID CiLib::HwlPadDimensions(
     UINT_32             bpp,         ///< [in] bits per pixel
     ADDR_SURFACE_FLAGS  flags,       ///< [in] surface flags
     UINT_32             numSamples,  ///< [in] number of samples
-    ADDR_TILEINFO*      pTileInfo,   ///< [in/out] bank structure.
+    ADDR_TILEINFO*      pTileInfo,   ///< [in,out] bank structure.
     UINT_32             padDims,     ///< [in] Dimensions to pad valid value 1,2,3
     UINT_32             mipLevel,    ///< [in] MipLevel
-    UINT_32*            pPitch,      ///< [in/out] pitch in pixels
+    UINT_32*            pPitch,      ///< [in,out] pitch in pixels
     UINT_32             pitchAlign,  ///< [in] pitch alignment
-    UINT_32*            pHeight,     ///< [in/out] height in pixels
+    UINT_32*            pHeight,     ///< [in,out] height in pixels
     UINT_32             heightAlign, ///< [in] height alignment
-    UINT_32*            pSlices,     ///< [in/out] number of slices
+    UINT_32*            pSlices,     ///< [in,out] number of slices
     UINT_32             sliceAlign   ///< [in] number of slice alignment
     ) const
 {
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 438790a5895..a9b1607ff1d 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -57,7 +57,7 @@ struct CIChipSettings
         UINT_32 isSpectre   : 1;
         UINT_32 isSpooky    : 1;
         UINT_32 isKalindi   : 1;
-        // Hawaii is GFXIP 7.2, similar with CI (Bonaire)
+        // Hawaii is GFXIP 7.2
         UINT_32 isHawaii    : 1;
 
         // VI
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 5de3f996f08..b15168263f3 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -27,7 +27,7 @@
 /**
 ****************************************************************************************************
 * @file  egbaddrlib.cpp
-* @brief Contains the EgBasedLib class implementation
+* @brief Contains the EgBasedLib class implementation.
 ****************************************************************************************************
 */
 
@@ -49,7 +49,8 @@ namespace V1
 *
 ****************************************************************************************************
 */
-EgBasedLib::EgBasedLib(const Client* pClient) :
+EgBasedLib::EgBasedLib(const Client* pClient)
+    :
     Lib(pClient),
     m_ranks(0),
     m_logicalBanks(0),
@@ -743,7 +744,7 @@ BOOL_32 EgBasedLib::HwlReduceBankWidthHeight(
     UINT_32             numSamples,         ///< [in] number of samples
     UINT_32             bankHeightAlign,    ///< [in] bank height alignment
     UINT_32             pipes,              ///< [in] pipes
-    ADDR_TILEINFO*      pTileInfo           ///< [in/out] bank structure.
+    ADDR_TILEINFO*      pTileInfo           ///< [in,out] bank structure.
     ) const
 {
     UINT_32 macroAspectAlign;
@@ -846,7 +847,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
     ADDR_SURFACE_FLAGS  flags,              ///< [in] surface flags
     UINT_32             mipLevel,           ///< [in] mip level
     UINT_32             numSamples,         ///< [in] number of samples
-    ADDR_TILEINFO*      pTileInfo,          ///< [in/out] bank structure.
+    ADDR_TILEINFO*      pTileInfo,          ///< [in,out] bank structure.
     UINT_32*            pBaseAlign,         ///< [out] base address alignment in bytes
     UINT_32*            pPitchAlign,        ///< [out] pitch alignment in pixels
     UINT_32*            pHeightAlign,       ///< [out] height alignment in pixels
@@ -1247,7 +1248,7 @@ BOOL_32 EgBasedLib::HwlDegradeBaseLevel(
 AddrTileMode EgBasedLib::HwlDegradeThickTileMode(
     AddrTileMode        baseTileMode,   ///< [in] base tile mode
     UINT_32             numSlices,      ///< [in] current number of slices
-    UINT_32*            pBytesPerTile   ///< [in/out] pointer to bytes per slice
+    UINT_32*            pBytesPerTile   ///< [in,out] pointer to bytes per slice
     ) const
 {
     ADDR_ASSERT(numSlices < Thickness(baseTileMode));
@@ -4755,8 +4756,8 @@ UINT_64 EgBasedLib::HwlGetSizeAdjustmentMicroTiled(
     UINT_32             numSamples,     ///< [in] number of samples
     UINT_32             baseAlign,      ///< [in] base alignment
     UINT_32             pitchAlign,     ///< [in] pitch alignment
-    UINT_32*            pPitch,         ///< [in/out] pointer to pitch
-    UINT_32*            pHeight         ///< [in/out] pointer to height
+    UINT_32*            pPitch,         ///< [in,out] pointer to pitch
+    UINT_32*            pHeight         ///< [in,out] pointer to height
     ) const
 {
     UINT_64 logicalSliceSize;
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index 9d3f5aa9367..f1f5a1bb9ec 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -1527,9 +1527,9 @@ UINT_64 SiLib::HwlGetSizeAdjustmentLinear(
     UINT_32             numSamples,     ///< [in] number of samples
     UINT_32             baseAlign,      ///< [in] base alignment
     UINT_32             pitchAlign,     ///< [in] pitch alignment
-    UINT_32*            pPitch,         ///< [in/out] pointer to pitch
-    UINT_32*            pHeight,        ///< [in/out] pointer to height
-    UINT_32*            pHeightAlign    ///< [in/out] pointer to height align
+    UINT_32*            pPitch,         ///< [in,out] pointer to pitch
+    UINT_32*            pHeight,        ///< [in,out] pointer to height
+    UINT_32*            pHeightAlign    ///< [in,out] pointer to height align
     ) const
 {
     UINT_64 sliceSize;
@@ -1682,8 +1682,8 @@ UINT_64 SiLib::HwlGetSizeAdjustmentMicroTiled(
     UINT_32             numSamples,     ///< [in] number of samples
     UINT_32             baseAlign,      ///< [in] base alignment
     UINT_32             pitchAlign,     ///< [in] pitch alignment
-    UINT_32*            pPitch,         ///< [in/out] pointer to pitch
-    UINT_32*            pHeight         ///< [in/out] pointer to height
+    UINT_32*            pPitch,         ///< [in,out] pointer to pitch
+    UINT_32*            pHeight         ///< [in,out] pointer to height
     ) const
 {
     UINT_64 logicalSliceSize;
@@ -2316,8 +2316,8 @@ UINT_32 SiLib::HwlComputeXmaskCoordYFrom8Pipe(
 */
 VOID SiLib::HwlComputeSurfaceCoord2DFromBankPipe(
     AddrTileMode        tileMode,   ///< [in] tile mode
-    UINT_32*            pX,         ///< [in/out] x coordinate
-    UINT_32*            pY,         ///< [in/out] y coordinate
+    UINT_32*            pX,         ///< [in,out] x coordinate
+    UINT_32*            pY,         ///< [in,out] y coordinate
     UINT_32             slice,      ///< [in] slice index
     UINT_32             bank,       ///< [in] bank number
     UINT_32             pipe,       ///< [in] pipe number
@@ -2555,7 +2555,7 @@ ADDR_E_RETURNCODE SiLib::HwlComputeSurfaceInfo(
 ****************************************************************************************************
 */
 BOOL_32 SiLib::HwlComputeMipLevel(
-    ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in/out] Input structure
+    ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn ///< [in,out] Input structure
     ) const
 {
     // basePitch is calculated from level 0 so we only check this for mipLevel > 0
@@ -2595,7 +2595,7 @@ BOOL_32 SiLib::HwlComputeMipLevel(
 */
 VOID SiLib::HwlCheckLastMacroTiledLvl(
     const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn, ///< [in] Input structure
-    ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut      ///< [in/out] Output structure (used as input, too)
+    ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut      ///< [in,out] Output structure (used as input, too)
     ) const
 {
     // pow2Pad covers all mipmap cases
@@ -2672,7 +2672,7 @@ VOID SiLib::HwlCheckLastMacroTiledLvl(
 AddrTileMode SiLib::HwlDegradeThickTileMode(
     AddrTileMode        baseTileMode,   ///< [in] base tile mode
     UINT_32             numSlices,      ///< [in] current number of slices
-    UINT_32*            pBytesPerTile   ///< [in/out] pointer to bytes per slice
+    UINT_32*            pBytesPerTile   ///< [in,out] pointer to bytes per slice
     ) const
 {
     return EgBasedLib::HwlDegradeThickTileMode(baseTileMode, numSlices, pBytesPerTile);
@@ -3146,7 +3146,7 @@ UINT_32 SiLib::HwlComputeFmaskBits(
 ****************************************************************************************************
 */
 VOID SiLib::HwlOverrideTileMode(
-    ADDR_COMPUTE_SURFACE_INFO_INPUT*    pInOut          ///< [in/out] input output structure
+    ADDR_COMPUTE_SURFACE_INFO_INPUT*    pInOut          ///< [in,out] input output structure
     ) const
 {
     AddrTileMode tileMode = pInOut->tileMode;
@@ -3216,7 +3216,7 @@ VOID SiLib::HwlOverrideTileMode(
 ****************************************************************************************************
 */
 VOID SiLib::HwlSelectTileMode(
-    ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut     ///< [in/out] input output structure
+    ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut     ///< [in,out] input output structure
     ) const
 {
     AddrTileMode tileMode;
@@ -3508,9 +3508,9 @@ VOID SiLib::InitEquationTable()
 ****************************************************************************************************
 */
 BOOL_32 SiLib::IsEquationSupported(
-    UINT_32        bpp,         ///< Bits per pixel
+    UINT_32    bpp,         ///< Bits per pixel
     TileConfig tileConfig,  ///< Tile config
-    INT_32         tileIndex    ///< Tile index
+    INT_32     tileIndex    ///< Tile index
     ) const
 {
     BOOL_32 supported = TRUE;