amdgpu/addrlib: add dccRamSizeAligned output flag

This flag indicates to the client if this level's DCC memory is aligned
or not. No aligned means there are padding to the end.

1 files changed, 5 insertions, 0 deletions

diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 776c8b5ce36..97ef3b6a8d1 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -247,6 +247,7 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo(
                                     HwlGetPipes(&pIn->tileInfo) *
                                     m_pipeInterleaveBytes;
         pOut->dccFastClearSize    = dccFastClearSize;
+        pOut->dccRamSizeAligned   = TRUE;
 
         ADDR_ASSERT(IsPow2(pOut->dccRamBaseAlign));
 
@@ -262,6 +263,10 @@ ADDR_E_RETURNCODE CiAddrLib::HwlComputeDccInfo(
             {
                 pOut->dccFastClearSize = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
             }
+            if ((pOut->dccRamSize & (dccRamSizeAlign - 1)) != 0)
+            {
+                pOut->dccRamSizeAligned = FALSE;
+            }
             pOut->dccRamSize          = PowTwoAlign(pOut->dccRamSize, dccRamSizeAlign);
             pOut->subLvlCompressible  = FALSE;
         }