diff options
| author | Marek Olšák <[email protected]> | 2017-03-14 22:32:25 +0100 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | 8a74140a21fe6b0d2e8a60b065b890f797f2db51 (patch) | |
| tree | 50c8ca7a23e6b2daf480cb8dcfc65158b7e970a5 /src/amd/addrlib/r800 | |
| parent | 7f160efcde41b52ad78e562316384373dab419e3 (diff) | |
amd/addrlib: silence warnings
Diffstat (limited to 'src/amd/addrlib/r800')
| -rw-r--r-- | src/amd/addrlib/r800/egbaddrlib.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp index 0cd27ada070..03f3a3146e4 100644 --- a/src/amd/addrlib/r800/egbaddrlib.cpp +++ b/src/amd/addrlib/r800/egbaddrlib.cpp @@ -978,7 +978,7 @@ BOOL_32 EgBasedLib::SanityCheckMacroTiled( ) const { BOOL_32 valid = TRUE; - UINT_32 numPipes = HwlGetPipes(pTileInfo); + //UINT_32 numPipes = HwlGetPipes(pTileInfo); switch (pTileInfo->banks) { @@ -4748,7 +4748,7 @@ UINT_64 EgBasedLib::HwlGetSizeAdjustmentMicroTiled( ) const { UINT_64 logicalSliceSize; - UINT_64 physicalSliceSize; + //UINT_64 physicalSliceSize; UINT_32 pitch = *pPitch; UINT_32 height = *pHeight; @@ -4757,7 +4757,7 @@ UINT_64 EgBasedLib::HwlGetSizeAdjustmentMicroTiled( logicalSliceSize = BITS_TO_BYTES(static_cast<UINT_64>(pitch) * height * bpp * numSamples); // Physical slice: multiplied by thickness - physicalSliceSize = logicalSliceSize * thickness; + //physicalSliceSize = logicalSliceSize * thickness; // // R800 will always pad physical slice size to baseAlign which is pipe_interleave_bytes |