amd/addrlib: second update for Vega10 + bug fixes

Highlights:
- Display needs tiled pitch alignment to be at least 32 pixels
- Implement Addr2ComputeDccAddrFromCoord().
- Macro-pixel packed formats don't support Z swizzle modes
- Pad pitch and base alignment of PRT + TEX1D to 64KB.
- Fix support for multimedia formats
- Fix a case "PRT" entries are not selected on SI.
- Fix wrong upper bits in equations for 3D resource.
- We can't support 2d array slice rotation in gfx8 swizzle pattern
- Set base alignment for PRT + non-xor swizzle mode resource to 64KB.
- Bug workaround for Z16 4x/8x and Z32 2x/4x/8x MSAA depth texture
- Add stereo support
- Optimize swizzle mode selection
- Report pitch and height in pixels for each mip
- Adjust bpp/expandX for format ADDR_FMT_GB_GR/ADDR_FMT_BG_RG
- Correct tcCompatible flag output for mipmap surface
- Other fixes and cleanups

Acked-by: Alex Deucher <[email protected]>
Acked-by: Nicolai Hähnle <[email protected]>

5 files changed, 93 insertions, 51 deletions

diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 1f7bb189fe4..fe965b8eebd 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -711,6 +711,15 @@ ADDR_E_RETURNCODE CiLib::HwlComputeSurfaceInfo(
 
     ADDR_E_RETURNCODE retCode = SiLib::HwlComputeSurfaceInfo(pIn, pOut);
 
+
+    if ((pIn->mipLevel > 0) &&
+        (pOut->tcCompatible == TRUE) &&
+        (pOut->tileMode != pIn->tileMode) &&
+        (m_settings.isVolcanicIslands == TRUE))
+    {
+        CheckTcCompatibility(pOut->pTileInfo, pIn->bpp, pOut->tileMode, pOut->tileType, pOut);
+    }
+
     if (pOut->macroModeIndex == TileIndexNoMacroIndex)
     {
         pOut->macroModeIndex = TileIndexInvalid;
@@ -1057,29 +1066,29 @@ VOID CiLib::HwlOverrideTileMode(
                     switch (tileMode)
                     {
                         case ADDR_TM_1D_TILED_THICK:
-                            tileMode    = ADDR_TM_1D_TILED_THIN1;
+                            tileMode = ADDR_TM_1D_TILED_THIN1;
                             break;
 
                         case ADDR_TM_2D_TILED_XTHICK:
                         case ADDR_TM_2D_TILED_THICK:
-                            tileMode    = ADDR_TM_2D_TILED_THIN1;
+                            tileMode = ADDR_TM_2D_TILED_THIN1;
                             break;
 
                         case ADDR_TM_3D_TILED_XTHICK:
                         case ADDR_TM_3D_TILED_THICK:
-                            tileMode    = ADDR_TM_3D_TILED_THIN1;
+                            tileMode = ADDR_TM_3D_TILED_THIN1;
                             break;
 
                         case ADDR_TM_PRT_TILED_THICK:
-                            tileMode    = ADDR_TM_PRT_TILED_THIN1;
+                            tileMode = ADDR_TM_PRT_TILED_THIN1;
                             break;
 
                         case ADDR_TM_PRT_2D_TILED_THICK:
-                            tileMode    = ADDR_TM_PRT_2D_TILED_THIN1;
+                            tileMode = ADDR_TM_PRT_2D_TILED_THIN1;
                             break;
 
                         case ADDR_TM_PRT_3D_TILED_THICK:
-                            tileMode    = ADDR_TM_PRT_3D_TILED_THIN1;
+                            tileMode = ADDR_TM_PRT_3D_TILED_THIN1;
                             break;
 
                         default:
@@ -1563,39 +1572,7 @@ VOID CiLib::HwlSetupTileInfo(
 
     if (flags.tcCompatible)
     {
-        if (IsMacroTiled(tileMode))
-        {
-            if (inTileType != ADDR_DEPTH_SAMPLE_ORDER)
-            {
-                // Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil
-                // tileSplit case was handled at tileIndex selecting time.
-                INT_32 tileIndex = pOut->tileIndex;
-
-                if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
-                {
-                    tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, inTileType, tileIndex);
-                }
-
-                if (tileIndex != TileIndexInvalid)
-                {
-                    ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
-                    // Non-depth entries store a split factor
-                    UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
-                    UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
-                    UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
-
-                    if (m_rowSize < colorTileSplit)
-                    {
-                        flags.tcCompatible = FALSE;
-                    }
-                }
-            }
-        }
-        else
-        {
-            // Client should not enable tc compatible for linear and 1D tile modes.
-            flags.tcCompatible = FALSE;
-        }
+        CheckTcCompatibility(pTileInfo, bpp, tileMode, inTileType, pOut);
     }
 
     pOut->tcCompatible = flags.tcCompatible;
@@ -2289,5 +2266,60 @@ BOOL_32 CiLib::DepthStencilTileCfgMatch(
     return depthStencil2DTileConfigMatch;
 }
 
+/**
+****************************************************************************************************
+*   CiLib::DepthStencilTileCfgMatch
+*
+*   @brief
+*       Turn off TcCompatible if requirement is not met
+*   @return
+*       N/A
+****************************************************************************************************
+*/
+VOID CiLib::CheckTcCompatibility(
+    const ADDR_TILEINFO*              pTileInfo,    ///< [in] input tile info
+    UINT_32                           bpp,          ///< [in] Bits per pixel
+    AddrTileMode                      tileMode,     ///< [in] input tile mode
+    AddrTileType                      tileType,     ///< [in] input tile type
+    ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut          ///< [out] out structure
+    ) const
+{
+    if (IsMacroTiled(tileMode))
+    {
+        if (tileType != ADDR_DEPTH_SAMPLE_ORDER)
+        {
+            // Turn off tcCompatible for color surface if tileSplit happens. Depth/stencil
+            // tileSplit case was handled at tileIndex selecting time.
+            INT_32 tileIndex = pOut->tileIndex;
+
+            if ((tileIndex == TileIndexInvalid) && (IsTileInfoAllZero(pTileInfo) == FALSE))
+            {
+                tileIndex = HwlPostCheckTileIndex(pTileInfo, tileMode, tileType, tileIndex);
+            }
+
+            if (tileIndex != TileIndexInvalid)
+            {
+                UINT_32 thickness = Thickness(tileMode);
+
+                ADDR_ASSERT(static_cast<UINT_32>(tileIndex) < TileTableSize);
+                // Non-depth entries store a split factor
+                UINT_32 sampleSplit = m_tileTable[tileIndex].info.tileSplitBytes;
+                UINT_32 tileBytes1x = BITS_TO_BYTES(bpp * MicroTilePixels * thickness);
+                UINT_32 colorTileSplit = Max(256u, sampleSplit * tileBytes1x);
+
+                if (m_rowSize < colorTileSplit)
+                {
+                    pOut->tcCompatible = FALSE;
+                }
+            }
+        }
+    }
+    else
+    {
+        // Client should not enable tc compatible for linear and 1D tile modes.
+        pOut->tcCompatible = FALSE;
+    }
+}
+
 } // V1
 } // Addr
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 48835b32822..7e331dd56cf 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -208,6 +208,10 @@ private:
         const ADDR_COMPUTE_SURFACE_INFO_INPUT*  pIn,
         ADDR_COMPUTE_SURFACE_INFO_OUTPUT*       pOut) const;
 
+    VOID CheckTcCompatibility(
+        const ADDR_TILEINFO* pTileInfo, UINT_32 bpp, AddrTileMode tileMode,
+         AddrTileType tileType, ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
+
     static const UINT_32    MacroTileTableSize = 16;
     static const UINT_32    PrtMacroModeOffset = MacroTileTableSize / 2;
     static const INT_32     MinDepth2DThinIndex = 0;
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index 0cd27ada070..7affdecbf02 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -4125,7 +4125,7 @@ UINT_32 EgBasedLib::ComputeFmaskResolvedBppFromNumSamples(
 ****************************************************************************************************
 */
 BOOL_32 EgBasedLib::IsTileInfoAllZero(
-    ADDR_TILEINFO* pTileInfo)
+    const ADDR_TILEINFO* pTileInfo)
 {
     BOOL_32 allZero = TRUE;
 
diff --git a/src/amd/addrlib/r800/egbaddrlib.h b/src/amd/addrlib/r800/egbaddrlib.h
index dbe712a6714..ee2c689df62 100644
--- a/src/amd/addrlib/r800/egbaddrlib.h
+++ b/src/amd/addrlib/r800/egbaddrlib.h
@@ -297,7 +297,7 @@ protected:
         ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const;
 
     // Static functions
-    static BOOL_32 IsTileInfoAllZero(ADDR_TILEINFO* pTileInfo);
+    static BOOL_32 IsTileInfoAllZero(const ADDR_TILEINFO* pTileInfo);
     static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples);
     static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples);
 
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index d358f0d10b2..ffa5488662b 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -2662,9 +2662,15 @@ ADDR_E_RETURNCODE SiLib::HwlComputeSurfaceInfo(
     {
         static const UINT_32 SiUncompressDepthTileIndex = 3;
 
-        if ((pIn->flags.prt == FALSE) &&
-            (m_uncompressDepthEqIndex != 0) &&
-            (tileIndex == SiUncompressDepthTileIndex))
+        if ((pIn->numSlices > 1) &&
+            (IsMacroTiled(pOut->tileMode) == TRUE) &&
+            (m_chipFamily == ADDR_CHIP_FAMILY_SI))
+        {
+            pOut->equationIndex = ADDR_INVALID_EQUATION_INDEX;
+        }
+        else if ((pIn->flags.prt == FALSE) &&
+                 (m_uncompressDepthEqIndex != 0) &&
+                 (tileIndex == SiUncompressDepthTileIndex))
         {
             pOut->equationIndex = m_uncompressDepthEqIndex + Log2(pIn->bpp >> 3);
         }
@@ -3344,19 +3350,19 @@ VOID SiLib::HwlOverrideTileMode(
     switch (tileMode)
     {
         case ADDR_TM_PRT_TILED_THIN1:
-            tileMode    = ADDR_TM_2D_TILED_THIN1;
+            tileMode = ADDR_TM_2D_TILED_THIN1;
             break;
 
         case ADDR_TM_PRT_TILED_THICK:
-            tileMode    = ADDR_TM_2D_TILED_THICK;
+            tileMode = ADDR_TM_2D_TILED_THICK;
             break;
 
         case ADDR_TM_PRT_2D_TILED_THICK:
-            tileMode    = ADDR_TM_2D_TILED_THICK;
+            tileMode = ADDR_TM_2D_TILED_THICK;
             break;
 
         case ADDR_TM_PRT_3D_TILED_THICK:
-            tileMode    = ADDR_TM_3D_TILED_THICK;
+            tileMode = ADDR_TM_3D_TILED_THICK;
             break;
 
         default:
@@ -3365,9 +3371,9 @@ VOID SiLib::HwlOverrideTileMode(
 
     if (tileMode != pInOut->tileMode)
     {
-        pInOut->tileMode = tileMode;
-
-        ADDR_ASSERT(pInOut->flags.prt == TRUE);
+        pInOut->tileMode  = tileMode;
+        // Only PRT tile modes are overridden for now. Revisit this once new modes are added above.
+        pInOut->flags.prt = TRUE;
     }
 }