amdgpu/addrlib: style changes and minor cleanups

Signed-off-by: Nicolai Hähnle <[email protected]>

6 files changed, 37 insertions, 32 deletions

diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp
index 1176ead49ba..776c8b5ce36 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -1859,3 +1859,4 @@ ADDR_E_RETURNCODE CiAddrLib::HwlGetMaxAlignments(
 
     return ADDR_OK;
 }
+
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 90d6c1b2b90..92d84683c14 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -128,13 +128,13 @@ protected:
         const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
         INT curIndex = TileIndexInvalid) const;
 
-    virtual VOID   HwlFmaskPreThunkSurfInfo(
+    virtual VOID HwlFmaskPreThunkSurfInfo(
         const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
         const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
         ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
         ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const;
 
-    virtual VOID   HwlFmaskPostThunkSurfInfo(
+    virtual VOID HwlFmaskPostThunkSurfInfo(
         const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
         ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;
 
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index b7c69956d8a..03ae41f0677 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -546,7 +546,7 @@ BOOL_32 EgBasedAddrLib::ComputeSurfaceInfoMacroTiled(
         // is needed.
         // The original height is pre-stored in pOut->height in PostComputeMipLevel and
         // pOut->pitch is needed in HwlCheckLastMacroTiledLvl, too.
-        if (m_configFlags.checkLast2DLevel && numSamples == 1) // Don't check MSAA
+        if (m_configFlags.checkLast2DLevel && (numSamples == 1)) // Don't check MSAA
         {
             // Set a TRUE in pOut if next Level is the first 1D sub level
             HwlCheckLastMacroTiledLvl(pIn, pOut);
@@ -765,7 +765,7 @@ BOOL_32 EgBasedAddrLib::HwlReduceBankWidthHeight(
         valid = !stillGreater;
 
         // Generate a warning if we still fail to meet this constraint
-        if (!valid)
+        if (valid == FALSE)
         {
             ADDR_WARN(
                 0, ("TILE_SIZE(%d)*BANK_WIDTH(%d)*BANK_HEIGHT(%d) <= ROW_SIZE(%d)",
@@ -1304,7 +1304,7 @@ UINT_64 EgBasedAddrLib::DispatchComputeSurfaceAddrFromCoord(
         /// @note
         /// 128 bit/thick tiled surface doesn't support display tiling and
         /// mipmap chain must have the same tileType, so please fill tileType correctly
-        if (!IsLinear(pIn->tileMode))
+        if (IsLinear(pIn->tileMode) == FALSE)
         {
             if (bpp >= 128 || ComputeSurfaceThickness(tileMode) > 1)
             {
@@ -2051,7 +2051,7 @@ VOID EgBasedAddrLib::DispatchComputeSurfaceCoordFromAddr(
         /// @note
         /// 128 bit/thick tiled surface doesn't support display tiling and
         /// mipmap chain must have the same tileType, so please fill tileType correctly
-        if (!IsLinear(pIn->tileMode))
+        if (IsLinear(pIn->tileMode) == FALSE)
         {
             if (bpp >= 128 || ComputeSurfaceThickness(tileMode) > 1)
             {
@@ -3378,7 +3378,7 @@ UINT_64 EgBasedAddrLib::ComputeFmaskAddrFromCoordMicroTiled(
     //
     // Compute the number of planes.
     //
-    if (!resolved)
+    if (resolved == FALSE)
     {
         effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
         effectiveBpp = numSamples;
@@ -3490,7 +3490,7 @@ UINT_64 EgBasedAddrLib::ComputeFmaskAddrFromCoordMacroTiled(
     //
     // Compute the number of planes.
     //
-    if (!resolved)
+    if (resolved == FALSE)
     {
         effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
         effectiveBpp = numSamples;
@@ -3603,7 +3603,7 @@ VOID EgBasedAddrLib::ComputeFmaskCoordFromAddrMicroTiled(
         numSamples = 4;
     }
 
-    if (!resolved)
+    if (resolved == FALSE)
     {
         effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
         effectiveBpp  = numSamples;
@@ -3698,7 +3698,7 @@ VOID EgBasedAddrLib::ComputeFmaskCoordFromAddrMacroTiled(
     //
     // Compute the number of planes.
     //
-    if (!resolved)
+    if (resolved == FALSE)
     {
         effectiveSamples = ComputeFmaskNumPlanesFromNumSamples(numSamples);
         effectiveBpp  = numSamples;
@@ -4295,7 +4295,7 @@ ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeSurfaceInfo(
             pOut->pTileInfo = &tileInfo;
         }
 
-        if (!DispatchComputeSurfaceInfo(pIn, pOut))
+        if (DispatchComputeSurfaceInfo(pIn, pOut) == FALSE)
         {
             retCode = ADDR_INVALIDPARAMS;
         }
@@ -4323,9 +4323,10 @@ ADDR_E_RETURNCODE EgBasedAddrLib::HwlComputeSurfaceInfo(
             if (IsMacroTiled(pOut->tileMode))
             {
                 // If a valid index is returned, then no pTileInfo is okay
-                ADDR_ASSERT(!m_configFlags.useTileIndex || pOut->tileIndex != TileIndexInvalid);
+                ADDR_ASSERT((m_configFlags.useTileIndex == FALSE) ||
+                            (pOut->tileIndex != TileIndexInvalid));
 
-                if (!IsTileInfoAllZero(pIn->pTileInfo))
+                if (IsTileInfoAllZero(pIn->pTileInfo) == FALSE)
                 {
                     // The initial value of pIn->pTileInfo is copied to tileInfo
                     // We do not expect any of these value to be changed nor any 0 of inputs
@@ -4525,7 +4526,7 @@ UINT_32 EgBasedAddrLib::HwlGetPitchAlignmentMicroTiled(
     // Note: this actually does not work for mipmap but mipmap depth texture is not really
     // sampled with mipmap.
     //
-    if (flags.depth && !flags.noStencil)
+    if (flags.depth && (flags.noStencil == FALSE))
     {
         bpp = 8;
     }
@@ -4615,3 +4616,4 @@ UINT_32 EgBasedAddrLib::HwlStereoCheckRightOffsetPadding(
 
     return stereoHeightAlign;
 }
+
diff --git a/src/amd/addrlib/r800/egbaddrlib.h b/src/amd/addrlib/r800/egbaddrlib.h
index b8eabd816ff..d43eca81aae 100644
--- a/src/amd/addrlib/r800/egbaddrlib.h
+++ b/src/amd/addrlib/r800/egbaddrlib.h
@@ -149,7 +149,7 @@ protected:
     /// Return Cmask block max
     virtual BOOL_32 HwlGetMaxCmaskBlockMax() const
     {
-        return 16383; // 14 bits
+        return 0x3FFF; // 14 bits, 0n16383
     }
 
     // Sub-hwl interface
@@ -325,7 +325,7 @@ private:
         const ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_INPUT* pIn,
         ADDR_COMPUTE_SURFACE_ADDRFROMCOORD_OUTPUT* pOut) const;
 
-    VOID    DispatchComputeSurfaceCoordFromAddr(
+    VOID DispatchComputeSurfaceCoordFromAddr(
         const ADDR_COMPUTE_SURFACE_COORDFROMADDR_INPUT* pIn,
         ADDR_COMPUTE_SURFACE_COORDFROMADDR_OUTPUT* pOut) const;
 
@@ -345,7 +345,7 @@ private:
         ADDR_TILEINFO* pTileInfo,
         UINT_32* pBitPosition) const;
 
-    VOID    ComputeSurfaceCoordFromAddrMacroTiled(
+    VOID ComputeSurfaceCoordFromAddrMacroTiled(
         UINT_64 addr, UINT_32 bitPosition,
         UINT_32 bpp, UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
         AddrTileMode tileMode, UINT_32 tileBase, UINT_32 compBits,
@@ -359,7 +359,7 @@ private:
         const ADDR_COMPUTE_FMASK_ADDRFROMCOORD_INPUT* pIn,
         ADDR_COMPUTE_FMASK_ADDRFROMCOORD_OUTPUT* pOut) const;
 
-    VOID    DispatchComputeFmaskCoordFromAddr(
+    VOID DispatchComputeFmaskCoordFromAddr(
         const ADDR_COMPUTE_FMASK_COORDFROMADDR_INPUT* pIn,
         ADDR_COMPUTE_FMASK_COORDFROMADDR_OUTPUT* pOut) const;
 
@@ -369,13 +369,13 @@ private:
         UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode,
         BOOL_32 resolved, UINT_32* pBitPosition) const;
 
-    VOID    ComputeFmaskCoordFromAddrMicroTiled(
+    VOID ComputeFmaskCoordFromAddrMicroTiled(
         UINT_64 addr, UINT_32 bitPosition,
         UINT_32 pitch, UINT_32 height, UINT_32 numSamples,
         AddrTileMode tileMode, BOOL_32 resolved,
         UINT_32* pX, UINT_32* pY, UINT_32* pSlice, UINT_32* pSample, UINT_32* pPlane) const;
 
-    VOID    ComputeFmaskCoordFromAddrMacroTiled(
+    VOID ComputeFmaskCoordFromAddrMacroTiled(
         UINT_64 addr, UINT_32 bitPosition,
         UINT_32 pitch, UINT_32 height, UINT_32 numSamples, AddrTileMode tileMode,
         UINT_32 pipeSwizzle, UINT_32 bankSwizzle,
diff --git a/src/amd/addrlib/r800/siaddrlib.cpp b/src/amd/addrlib/r800/siaddrlib.cpp
index 2b7e9c9bd49..869cc56c1fe 100644
--- a/src/amd/addrlib/r800/siaddrlib.cpp
+++ b/src/amd/addrlib/r800/siaddrlib.cpp
@@ -1252,7 +1252,7 @@ UINT_32 SiAddrLib::HwlPreHandleBaseLvl3xPitch(
 
     // From SI, if pow2Pad is 1 the pitch is expanded 3x first, then padded to pow2, so nothing to
     // do here
-    if (!pIn->flags.pow2Pad)
+    if (pIn->flags.pow2Pad == FALSE)
     {
         AddrLib1::HwlPreHandleBaseLvl3xPitch(pIn, expPitch);
     }
@@ -1285,7 +1285,7 @@ UINT_32 SiAddrLib::HwlPostHandleBaseLvl3xPitch(
      *  be able to compute a correct pitch from it as h/w address library is doing the job.
      */
     // From SI, the pitch is expanded 3x first, then padded to pow2, so no special handler here
-    if (!pIn->flags.pow2Pad)
+    if (pIn->flags.pow2Pad == FALSE)
     {
         AddrLib1::HwlPostHandleBaseLvl3xPitch(pIn, expPitch);
     }
@@ -1378,7 +1378,7 @@ UINT_64 SiAddrLib::HwlGetSizeAdjustmentMicroTiled(
     // Note: this actually does not work for mipmap but mipmap depth texture is not really
     // sampled with mipmap.
     //
-    if (flags.depth && !flags.noStencil)
+    if (flags.depth && (flags.noStencil == FALSE))
     {
         ADDR_ASSERT(numSamples == 1);
 
@@ -1465,7 +1465,7 @@ VOID SiAddrLib::HwlSetupTileInfo(
     INT index = TileIndexInvalid;
 
     // Fail-safe code
-    if (!IsLinear(tileMode))
+    if (IsLinear(tileMode) == FALSE)
     {
         // 128 bpp/thick tiling must be non-displayable.
         // Fmask reuse color buffer's entry but bank-height field can be from another entry
@@ -2196,11 +2196,12 @@ BOOL_32 SiAddrLib::HwlComputeMipLevel(
         // Note: Don't check expand 3x formats(96 bit) as the basePitch is not pow2 even if
         // we explicity set pow2Pad flag. The 3x base pitch is padded to pow2 but after being
         // divided by expandX factor (3) - to program texture pitch, the basePitch is never pow2.
-        if (!AddrElemLib::IsExpand3x(pIn->format))
+        if (AddrElemLib::IsExpand3x(pIn->format) == FALSE)
         {
             // Sublevel pitches are generated from base level pitch instead of width on SI
             // If pow2Pad is 0, we don't assert - as this is not really used for a mip chain
-            ADDR_ASSERT(!pIn->flags.pow2Pad || ((pIn->basePitch != 0) && IsPow2(pIn->basePitch)));
+            ADDR_ASSERT((pIn->flags.pow2Pad == FALSE) ||
+                        ((pIn->basePitch != 0) && IsPow2(pIn->basePitch)));
         }
 
         if (pIn->basePitch != 0)
@@ -2386,7 +2387,7 @@ INT_32 SiAddrLib::HwlPostCheckTileIndex(
         // 3. tile info does not match for macro tiled
         if ((index == TileIndexInvalid         ||
             (mode != m_tileTable[index].mode)  ||
-            (macroTiled && !HwlTileInfoEqual(pInfo, &m_tileTable[index].info))))
+            (macroTiled && (HwlTileInfoEqual(pInfo, &m_tileTable[index].info) == FALSE))))
         {
             for (index = 0; index < static_cast<INT_32>(m_noOfEntries); index++)
             {
@@ -2446,7 +2447,7 @@ ADDR_E_RETURNCODE SiAddrLib::HwlSetupTileCfg(
     INT_32          macroModeIndex, ///< [in] Index in macro tile mode table(CI)
     ADDR_TILEINFO*  pInfo,          ///< [out] Tile Info
     AddrTileMode*   pMode,          ///< [out] Tile mode
-    AddrTileType*   pType          ///< [out] Tile type
+    AddrTileType*   pType           ///< [out] Tile type
     ) const
 {
     ADDR_E_RETURNCODE returnCode = ADDR_OK;
@@ -2684,7 +2685,7 @@ UINT_32 SiAddrLib::HwlComputeFmaskBits(
     {
         ADDR_ASSERT(numFrags <= 8);
 
-        if (!pIn->resolved)
+        if (pIn->resolved == FALSE)
         {
             if (numFrags == 1)
             {
@@ -2745,7 +2746,7 @@ UINT_32 SiAddrLib::HwlComputeFmaskBits(
     }
     else // Normal AA
     {
-        if (!pIn->resolved)
+        if (pIn->resolved == FALSE)
         {
             bpp          = ComputeFmaskNumPlanesFromNumSamples(numSamples);
             numSamples   = numSamples == 2 ? 8 : numSamples;
@@ -2861,3 +2862,4 @@ ADDR_E_RETURNCODE SiAddrLib::HwlGetMaxAlignments(
 
     return ADDR_OK;
 }
+
diff --git a/src/amd/addrlib/r800/siaddrlib.h b/src/amd/addrlib/r800/siaddrlib.h
index ba1d4b5466a..50373ccec75 100644
--- a/src/amd/addrlib/r800/siaddrlib.h
+++ b/src/amd/addrlib/r800/siaddrlib.h
@@ -205,13 +205,13 @@ protected:
         const ADDR_TILEINFO* pInfo, AddrTileMode mode, AddrTileType type,
         INT curIndex = TileIndexInvalid) const;
 
-    virtual VOID   HwlFmaskPreThunkSurfInfo(
+    virtual VOID HwlFmaskPreThunkSurfInfo(
         const ADDR_COMPUTE_FMASK_INFO_INPUT* pFmaskIn,
         const ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut,
         ADDR_COMPUTE_SURFACE_INFO_INPUT* pSurfIn,
         ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut) const;
 
-    virtual VOID   HwlFmaskPostThunkSurfInfo(
+    virtual VOID HwlFmaskPostThunkSurfInfo(
         const ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pSurfOut,
         ADDR_COMPUTE_FMASK_INFO_OUTPUT* pFmaskOut) const;