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authorNicolai Hähnle <[email protected]>2016-07-20 21:30:56 +0200
committerMarek Olšák <[email protected]>2017-03-30 14:44:33 +0200
commitfbc9ba7559b15d29cd8dc38dfb3751845ef3fd37 (patch)
treea2f41c4e5870de65a0328f0cda3061dc98156c34 /src/amd/addrlib/r800/egbaddrlib.h
parent145750efba609bc03d6216f9e08fed18bf3a1498 (diff)
amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji
The change also modifies function CiLib::HwlPadDimensions to report adjusted pitch alignment.
Diffstat (limited to 'src/amd/addrlib/r800/egbaddrlib.h')
-rw-r--r--src/amd/addrlib/r800/egbaddrlib.h8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/amd/addrlib/r800/egbaddrlib.h b/src/amd/addrlib/r800/egbaddrlib.h
index c397cfc4f81..1a560033681 100644
--- a/src/amd/addrlib/r800/egbaddrlib.h
+++ b/src/amd/addrlib/r800/egbaddrlib.h
@@ -300,6 +300,14 @@ protected:
static UINT_32 ComputeFmaskNumPlanesFromNumSamples(UINT_32 numSamples);
static UINT_32 ComputeFmaskResolvedBppFromNumSamples(UINT_32 numSamples);
+ virtual VOID HwlComputeSurfaceAlignmentsMacroTiled(
+ AddrTileMode tileMode, UINT_32 bpp, ADDR_SURFACE_FLAGS flags,
+ UINT_32 mipLevel, UINT_32 numSamples, ADDR_TILEINFO* pTileInfo,
+ UINT_32* pBaseAlign, UINT_32* pPitchAlign, UINT_32* pHeightAlign,
+ UINT_32* pMacroTileWidth, UINT_32* pMacroTileHeight) const
+ {
+ }
+
private:
BOOL_32 ComputeSurfaceInfoLinear(