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authorNicolai Hähnle <[email protected]>2016-07-20 21:30:56 +0200
committerMarek Olšák <[email protected]>2017-03-30 14:44:33 +0200
commitfbc9ba7559b15d29cd8dc38dfb3751845ef3fd37 (patch)
treea2f41c4e5870de65a0328f0cda3061dc98156c34 /src/amd/addrlib/r800/egbaddrlib.cpp
parent145750efba609bc03d6216f9e08fed18bf3a1498 (diff)
amdgpu/addrlib: Pad pitch to multiples of 256 for DCC surface on Fiji
The change also modifies function CiLib::HwlPadDimensions to report adjusted pitch alignment.
Diffstat (limited to 'src/amd/addrlib/r800/egbaddrlib.cpp')
-rw-r--r--src/amd/addrlib/r800/egbaddrlib.cpp25
1 files changed, 6 insertions, 19 deletions
diff --git a/src/amd/addrlib/r800/egbaddrlib.cpp b/src/amd/addrlib/r800/egbaddrlib.cpp
index b15168263f3..9655c47f7a8 100644
--- a/src/amd/addrlib/r800/egbaddrlib.cpp
+++ b/src/amd/addrlib/r800/egbaddrlib.cpp
@@ -264,7 +264,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoLinear(
pOut->pTileInfo,
padDims,
pIn->mipLevel,
- &expPitch, pOut->pitchAlign,
+ &expPitch, &pOut->pitchAlign,
&expHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
@@ -378,7 +378,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMicroTiled(
pOut->pTileInfo,
padDims,
pIn->mipLevel,
- &expPitch, pOut->pitchAlign,
+ &expPitch, &pOut->pitchAlign,
&expHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
@@ -527,7 +527,7 @@ BOOL_32 EgBasedLib::ComputeSurfaceInfoMacroTiled(
pOut->pTileInfo,
padDims,
pIn->mipLevel,
- &paddedPitch, pOut->pitchAlign,
+ &paddedPitch, &pOut->pitchAlign,
&paddedHeight, pOut->heightAlign,
&expNumSlices, microTileThickness);
@@ -932,22 +932,9 @@ BOOL_32 EgBasedLib::ComputeSurfaceAlignmentsMacroTiled(
*pBaseAlign = pipes *
pTileInfo->bankWidth * pTileInfo->banks * pTileInfo->bankHeight * tileSize;
- if ((mipLevel == 0) && (flags.prt) && (m_chipFamily == ADDR_CHIP_FAMILY_SI))
- {
- static const UINT_32 PrtTileSize = 0x10000;
-
- UINT_32 macroTileSize = macroTileWidth * macroTileHeight * numSamples * bpp / 8;
-
- if (macroTileSize < PrtTileSize)
- {
- UINT_32 numMacroTiles = PrtTileSize / macroTileSize;
-
- ADDR_ASSERT((PrtTileSize % macroTileSize) == 0);
-
- *pPitchAlign *= numMacroTiles;
- *pBaseAlign *= numMacroTiles;
- }
- }
+ HwlComputeSurfaceAlignmentsMacroTiled(tileMode, bpp, flags, mipLevel, numSamples,
+ pTileInfo, pBaseAlign, pPitchAlign, pHeightAlign,
+ pMacroTileWidth, pMacroTileHeight);
}
return valid;