diff options
| author | Frans Gu <[email protected]> | 2015-08-17 23:56:23 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | fe216415c69091ac27a10daafa3cd4ba0e205c6d (patch) | |
| tree | 954e8b355bd45ad2d56f2fdb0cd8075070eed4cc /src/amd/addrlib/r800/ciaddrlib.h | |
| parent | 4dd4700612adf7cb089eb667f265b7c55fd6fd7c (diff) | |
amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlign
1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger
than 1D
2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than
requested alignment.
Also, related changes to tile mode optimization for needEquation.
Diffstat (limited to 'src/amd/addrlib/r800/ciaddrlib.h')
| -rw-r--r-- | src/amd/addrlib/r800/ciaddrlib.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h index f6c865536ce..7fa6b75e864 100644 --- a/src/amd/addrlib/r800/ciaddrlib.h +++ b/src/amd/addrlib/r800/ciaddrlib.h @@ -149,8 +149,13 @@ protected: virtual VOID HwlOverrideTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const; + virtual VOID HwlOptimizeTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const; + virtual VOID HwlSelectTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const; + /// Overwrite tile setting to PRT + virtual VOID HwlSetPrtTileMode(ADDR_COMPUTE_SURFACE_INFO_INPUT* pInOut) const; + virtual ADDR_E_RETURNCODE HwlComputeDccInfo( const ADDR_COMPUTE_DCCINFO_INPUT* pIn, ADDR_COMPUTE_DCCINFO_OUTPUT* pOut) const; |