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authorXavi Zhang <[email protected]>2016-03-01 03:40:15 -0500
committerMarek Olšák <[email protected]>2017-03-30 14:44:33 +0200
commitfa906a888ba908611086e5e80a19bbb99618945d (patch)
treea747ce21d0dafddb65d9b2c7e27890bf86b95a71 /src/amd/addrlib/r800/ciaddrlib.h
parent6764d96eaaebc641c81cfc5666d99e8aa6ae698c (diff)
amdgpu/addrlib: add matchStencilTileCfg and tcCompatible fixes
The usage should be client first call AddrComputeSurfaceInfo() on depth surface with flag "matchStencilTilecfg", AddrLib will use 2DThin1 tile index for depth as much as possible and do not down grade unless alignment requirement cannot be met. 1. If there is a matched 2DThin1 tile index for stencil which make sure they will share same tile config parameters, then return the stencil 2DThin1 tile index as well. 2. If using 2DThin1 tile mode cannot make sure such thing happen, and TcCompatible flag was set, then ignore this flag then try 2DThin1 tile mode for depth and stencil again. 3. If 2DThin1 tile mode cannot make sure depth and stencil to have same tile config parameters, then down grade depth surface tile mode to 1DThin1. 4. If depth surface's tile mode was 1DThin1, then return 1DThin1 tile index for stencil. 5. If depth surface's tile mode is PRT, then return invalid tile index to stencil since their tile config parameters will never be met. Client driver then check the returned tile index of stencil -- if it is not invalid tile index, then call AddrComputeSurfaceInfo() on stencil surface with the returned stencil tile index to get full output information. Please note, client needs to set flag "useTileIndex" when AddrLib get created.
Diffstat (limited to 'src/amd/addrlib/r800/ciaddrlib.h')
-rw-r--r--src/amd/addrlib/r800/ciaddrlib.h7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index 93b2853d066..48835b32822 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -204,8 +204,15 @@ private:
UINT_32 numOfBanks,
UINT_32 numOfSamplesPerSplit) const;
+ BOOL_32 DepthStencilTileCfgMatch(
+ const ADDR_COMPUTE_SURFACE_INFO_INPUT* pIn,
+ ADDR_COMPUTE_SURFACE_INFO_OUTPUT* pOut) const;
+
static const UINT_32 MacroTileTableSize = 16;
static const UINT_32 PrtMacroModeOffset = MacroTileTableSize / 2;
+ static const INT_32 MinDepth2DThinIndex = 0;
+ static const INT_32 MaxDepth2DThinIndex = 4;
+ static const INT_32 Depth1DThinIndex = 5;
ADDR_TILEINFO m_macroTileTable[MacroTileTableSize];
UINT_32 m_noOfMacroEntries;