diff options
| author | Nicolai Hähnle <[email protected]> | 2016-07-20 10:33:44 +0200 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | a136926eef082963e0025ac5e44eff9f2d931663 (patch) | |
| tree | 1a08949877f061c7cb8d6b7c9a82cf9d4ab011d7 /src/amd/addrlib/r800/ciaddrlib.cpp | |
| parent | 48bf5d0800ef394879a5a229ac2ae5a15a4c75e5 (diff) | |
amdgpu/addrlib: Seperate 2 dcc related workarounds by different flags
1) dccCompatible for padding MSAA surface to support fast clear
2) dccPipeWorkaround for padding surface to support dcc
Diffstat (limited to 'src/amd/addrlib/r800/ciaddrlib.cpp')
| -rw-r--r-- | src/amd/addrlib/r800/ciaddrlib.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp b/src/amd/addrlib/r800/ciaddrlib.cpp index 5ccc5da4197..1f7bb189fe4 100644 --- a/src/amd/addrlib/r800/ciaddrlib.cpp +++ b/src/amd/addrlib/r800/ciaddrlib.cpp @@ -979,7 +979,7 @@ VOID CiLib::HwlOptimizeTileMode( if (pInOut->maxBaseAlign != 0) { - pInOut->flags.dccCompatible = FALSE; + pInOut->flags.dccPipeWorkaround = FALSE; } } @@ -2095,7 +2095,7 @@ VOID CiLib::HwlComputeSurfaceAlignmentsMacroTiled( // P4. In theory, all asics that have such switching should be patched but we now only know what // to pad for Fiji. if ((m_settings.isFiji == TRUE) && - (flags.dccCompatible == TRUE) && + (flags.dccPipeWorkaround == TRUE) && (flags.prt == FALSE) && (mipLevel == 0) && (tileMode == ADDR_TM_PRT_TILED_THIN1) && |