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authorBas Nieuwenhuizen <[email protected]>2018-03-28 23:54:40 +0200
committerBas Nieuwenhuizen <[email protected]>2018-03-29 00:03:03 +0200
commit4503ff760c794c3bb15b978a47c530037d56498e (patch)
treedfff19da4d0e66103c33a95da776a9b41b945d62 /src/amd/addrlib/inc
parent4f96747530be799e3ccd84ccf48df6d7fdbd0a03 (diff)
ac/nir: Add workaround for GFX9 buffer views.
On GFX9 whether the buffer size is interpreted as elements or bytes depends on whether IDXEN is enabled in the instruction. If the index is a constant zero, LLVM optimizes IDXEN to 0. Now the size in elements is interpreted in bytes which of course results in out of bounds accesses. The correct fix is most likely to disable the LLVM optimization, but we need something to work with LLVM <= 6.0. radeonsi does the max between stride and element count on the CPU but that results in the size intrinsics returning the wrong size for the buffer. This would cause CTS errors for radv. v2: Also include the store changes. Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."' Reviewed-by: Samuel Pitoiset <[email protected]>
Diffstat (limited to 'src/amd/addrlib/inc')
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