diff options
author | Marek Olšák <[email protected]> | 2019-06-14 17:55:38 -0400 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2019-06-17 15:14:55 -0400 |
commit | eba932ea43a702e097218d2d4b1df56e0d1e3940 (patch) | |
tree | 14fa344b7e5553d2468575303b2f4f8a052c7eb5 /src/amd/addrlib/inc | |
parent | d15cc1f55a7fa511d62124c1b4dd7f12c0ab240c (diff) |
amd: update addrlib
Acked-by: Bas Nieuwenhuizen <[email protected]>
Tested-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/amd/addrlib/inc')
-rw-r--r-- | src/amd/addrlib/inc/addrinterface.h | 12 | ||||
-rw-r--r-- | src/amd/addrlib/inc/addrtypes.h | 36 |
2 files changed, 27 insertions, 21 deletions
diff --git a/src/amd/addrlib/inc/addrinterface.h b/src/amd/addrlib/inc/addrinterface.h index 1a2690970be..8e8f36378b3 100644 --- a/src/amd/addrlib/inc/addrinterface.h +++ b/src/amd/addrlib/inc/addrinterface.h @@ -1,5 +1,5 @@ /* - * Copyright © 2007-2018 Advanced Micro Devices, Inc. + * Copyright © 2007-2019 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining @@ -307,7 +307,8 @@ typedef union _ADDR_CREATE_FLAGS UINT_32 checkLast2DLevel : 1; ///< Check the last 2D mip sub level UINT_32 useHtileSliceAlign : 1; ///< Do htile single slice alignment UINT_32 allowLargeThickTile : 1; ///< Allow 64*thickness*bytesPerPixel > rowSize - UINT_32 reserved : 25; ///< Reserved bits for future use + UINT_32 forceDccAndTcCompat : 1; ///< Force enable DCC and TC compatibility + UINT_32 reserved : 24; ///< Reserved bits for future use }; UINT_32 value; @@ -2879,6 +2880,9 @@ typedef struct _ADDR2_COMPUTE_CMASKINFO_INPUT UINT_32 unalignedWidth; ///< Color surface original width UINT_32 unalignedHeight; ///< Color surface original height UINT_32 numSlices; ///< Number of slices of color buffer + UINT_32 numMipLevels; ///< Number of mip levels + UINT_32 firstMipIdInTail; ///< The id of first mip in tail, if no mip is in tail, + /// it should be number of mip levels } ADDR2_COMPUTE_CMASK_INFO_INPUT; /** @@ -2904,7 +2908,9 @@ typedef struct _ADDR2_COMPUTE_CMASK_INFO_OUTPUT UINT_32 metaBlkWidth; ///< Meta block width UINT_32 metaBlkHeight; ///< Meta block height - UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice + UINT_32 metaBlkNumPerSlice; ///< Number of metablock within one slice + + ADDR2_META_MIP_INFO* pMipInfo; ///< CMASK mip information } ADDR2_COMPUTE_CMASK_INFO_OUTPUT; /** diff --git a/src/amd/addrlib/inc/addrtypes.h b/src/amd/addrlib/inc/addrtypes.h index c9393579b7e..36e342f3176 100644 --- a/src/amd/addrlib/inc/addrtypes.h +++ b/src/amd/addrlib/inc/addrtypes.h @@ -1,5 +1,5 @@ /* - * Copyright © 2007-2018 Advanced Micro Devices, Inc. + * Copyright © 2007-2019 Advanced Micro Devices, Inc. * All Rights Reserved. * * Permission is hereby granted, free of charge, to any person obtaining @@ -567,23 +567,23 @@ typedef enum _AddrHtileBlockSize */ typedef enum _AddrPipeCfg { - ADDR_PIPECFG_INVALID = 0, - ADDR_PIPECFG_P2 = 1, /// 2 pipes, - ADDR_PIPECFG_P4_8x16 = 5, /// 4 pipes, - ADDR_PIPECFG_P4_16x16 = 6, - ADDR_PIPECFG_P4_16x32 = 7, - ADDR_PIPECFG_P4_32x32 = 8, - ADDR_PIPECFG_P8_16x16_8x16 = 9, /// 8 pipes - ADDR_PIPECFG_P8_16x32_8x16 = 10, - ADDR_PIPECFG_P8_32x32_8x16 = 11, - ADDR_PIPECFG_P8_16x32_16x16 = 12, - ADDR_PIPECFG_P8_32x32_16x16 = 13, - ADDR_PIPECFG_P8_32x32_16x32 = 14, - ADDR_PIPECFG_P8_32x64_32x32 = 15, - ADDR_PIPECFG_P16_32x32_8x16 = 17, /// 16 pipes - ADDR_PIPECFG_P16_32x32_16x16 = 18, - ADDR_PIPECFG_RESERVED = 19, /// reserved for internal use - ADDR_PIPECFG_MAX = 20, + ADDR_PIPECFG_INVALID = 0, + ADDR_PIPECFG_P2 = 1, /// 2 pipes, + ADDR_PIPECFG_P4_8x16 = 5, /// 4 pipes, + ADDR_PIPECFG_P4_16x16 = 6, + ADDR_PIPECFG_P4_16x32 = 7, + ADDR_PIPECFG_P4_32x32 = 8, + ADDR_PIPECFG_P8_16x16_8x16 = 9, /// 8 pipes + ADDR_PIPECFG_P8_16x32_8x16 = 10, + ADDR_PIPECFG_P8_32x32_8x16 = 11, + ADDR_PIPECFG_P8_16x32_16x16 = 12, + ADDR_PIPECFG_P8_32x32_16x16 = 13, + ADDR_PIPECFG_P8_32x32_16x32 = 14, + ADDR_PIPECFG_P8_32x64_32x32 = 15, + ADDR_PIPECFG_P16_32x32_8x16 = 17, /// 16 pipes + ADDR_PIPECFG_P16_32x32_16x16 = 18, + ADDR_PIPECFG_UNUSED = 19, + ADDR_PIPECFG_MAX = 20, } AddrPipeCfg; /** |