diff options
| author | Frans Gu <[email protected]> | 2015-08-17 23:56:23 -0400 |
|---|---|---|
| committer | Marek Olšák <[email protected]> | 2017-03-30 14:44:33 +0200 |
| commit | fe216415c69091ac27a10daafa3cd4ba0e205c6d (patch) | |
| tree | 954e8b355bd45ad2d56f2fdb0cd8075070eed4cc /src/amd/addrlib/addrinterface.h | |
| parent | 4dd4700612adf7cb089eb667f265b7c55fd6fd7c (diff) | |
amdgpu/addrlib: Add new flags minimizePadding and maxBaseAlign
1) minimizePadding - Use 1D tile mode if padded size of 2D is bigger
than 1D
2) maxBaseAlign - Force PRT tile mode if macro block size is bigger than
requested alignment.
Also, related changes to tile mode optimization for needEquation.
Diffstat (limited to 'src/amd/addrlib/addrinterface.h')
| -rw-r--r-- | src/amd/addrlib/addrinterface.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h index a2a36cd1173..065545e8f01 100644 --- a/src/amd/addrlib/addrinterface.h +++ b/src/amd/addrlib/addrinterface.h @@ -515,7 +515,8 @@ typedef union _ADDR_SURFACE_FLAGS /// which is needed by swizzle pattern equation. UINT_32 skipIndicesOutput : 1; ///< Skipping indices in output. UINT_32 rotateDisplay : 1; ///< Rotate micro tile type - UINT_32 reserved : 6; ///< Reserved bits + UINT_32 minimizeAlignment : 1; ///< Minimize alignment + UINT_32 reserved : 5; ///< Reserved bits }; UINT_32 value; @@ -557,6 +558,9 @@ typedef struct _ADDR_COMPUTE_SURFACE_INFO_INPUT UINT_32 basePitch; ///< Base level pitch in pixels, 0 means ignored, is a /// must for mip levels from SI+. /// Don't use pitch in blocks for compressed formats! + UINT_32 maxBaseAlign; ///< Max base alignment request from client + UINT_32 pitchAlign; ///< Pitch alignment request from client + UINT_32 heightAlign; ///< Height alignment request from client } ADDR_COMPUTE_SURFACE_INFO_INPUT; /** |