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authorXavi Zhang <[email protected]>2014-11-24 22:49:50 -0500
committerMarek Olšák <[email protected]>2017-03-30 14:44:33 +0200
commit2bf243f7c6fdea49737a27923d7ed24bb835de22 (patch)
tree4f487e9e27d50774805d58cc8a32868bb9d7f2f3 /src/amd/addrlib/addrinterface.h
parente443b4896645ef30b93f3c801679d295d76175f0 (diff)
amdgpu/addrlib: add dccRamSizeAligned output flag
This flag indicates to the client if this level's DCC memory is aligned or not. No aligned means there are padding to the end.
Diffstat (limited to 'src/amd/addrlib/addrinterface.h')
-rw-r--r--src/amd/addrlib/addrinterface.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/amd/addrlib/addrinterface.h b/src/amd/addrlib/addrinterface.h
index d94518fd769..bd10310dad2 100644
--- a/src/amd/addrlib/addrinterface.h
+++ b/src/amd/addrlib/addrinterface.h
@@ -2128,7 +2128,8 @@ typedef struct _ADDR_COMPUTE_DCCINFO_OUTPUT
UINT_64 dccRamBaseAlign; ///< Base alignment of dcc key
UINT_64 dccRamSize; ///< Size of dcc key
UINT_64 dccFastClearSize; ///< Size of dcc key portion that can be fast cleared
- BOOL_32 subLvlCompressible; ///< whether sub resource is compressiable
+ BOOL_32 subLvlCompressible; ///< Whether sub resource is compressiable
+ BOOL_32 dccRamSizeAligned; ///< Whether the dcc key size is aligned
} ADDR_COMPUTE_DCCINFO_OUTPUT;
/**