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author | Jordan Justen <[email protected]> | 2016-04-02 01:25:05 -0700 |
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committer | Jordan Justen <[email protected]> | 2016-05-17 13:04:03 -0700 |
commit | ff417388719828b3b5f0c9e3c0b076e9cff99ff7 (patch) | |
tree | a6966c5f7d87f9dd540dc366eb462f77dc1474d1 /scons/source_list.py | |
parent | 47b390fe45e5e6f982c60b58985892438959cd8e (diff) |
genxml/hsw: Add L3 cache control registers
These were added to the i965 driver in
5912da45a69923afa1b7f2eb5bb371d848813c41.
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'scons/source_list.py')
0 files changed, 0 insertions, 0 deletions