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| author | Juan A. Suarez Romero <[email protected]> | 2016-08-03 11:51:44 +0000 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2017-04-14 14:56:07 -0700 |
| commit | 3198ce3f96848856206e7b2e54a53024bcca7737 (patch) | |
| tree | e5808af7f3fd115980b42c8d97ac8f572c20f03e /scons/crossmingw.py | |
| parent | 571cbd05ebfb8bef22277c5758afc82f5dd6a3f2 (diff) | |
i965/fs: fix lower SIMD width for IVB/BYT's MOV_INDIRECT
According to the IVB and HSW PRMs:
"2.When the destination requires two registers and the sources are
indirect, the sources must use 1x1 regioning mode."
So for DF instructions the execution size is not limited by the number
of address registers that are available, but by the EU decompression
logic not handling VxH indirect addressing correctly.
This patch limits the SIMD width to 4 in this case.
v2:
- Fix typo (Matt).
- Fix condition (Curro)
v3:
- Add spec quote (Curro)
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Signed-off-by: Juan A. Suarez Romero <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Diffstat (limited to 'scons/crossmingw.py')
0 files changed, 0 insertions, 0 deletions