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authorPierre Moreau <[email protected]>2017-12-03 21:28:57 +0100
committerIlia Mirkin <[email protected]>2017-12-04 01:03:47 -0500
commit9bee12160bed72dae5cdb006ea38c40f89e174da (patch)
treefffc6593e76b5c7a05f243b180118e46901496fe /meson.build
parent9bdb5457f4ecabd59e05d0b6cea1ff88bcb49d7f (diff)
nvc0/ir: Properly lower 64-bit shifts when the shift value is >32
Fixes: 61d7676df77 "nvc0/ir: add support for 64-bit shift lowering on SM20/SM30" Fixes fs-shift-scalar-by-scalar.shader_test from piglit for the current set-up: uniform int64_t ival -0x7dfcfefbdf6536ff # bit pattern: 0x82030104209ac901 uniform uint64_t uval 0x1400000085010203 uniform int shl 36 uniform int shr 36 uniform int64_t iexpected_shl 0x09ac901000000000 uniform int64_t iexpected_shr -0x7dfcff0 # bit pattern: 0xfffffffff8203010 uniform uint64_t uexpected_shl 0x5010203000000000 uniform uint64_t uexpected_shr 0x0000000001400000 draw rect ortho 12 0 4 4 Signed-off-by: Pierre Moreau <[email protected]> Reviewed-by: Ilia Mirkin <[email protected]>
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