diff options
author | Eric Anholt <[email protected]> | 2015-02-06 17:16:29 -0800 |
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committer | Eric Anholt <[email protected]> | 2015-02-11 11:52:38 -0800 |
commit | 2919bdf466295bc3fbf6f6e796ef8d301404d3d9 (patch) | |
tree | 114498d9d8ccb6745176a5c7e400698172d257c6 /m4 | |
parent | 09d6ea9ae3c487be20fb3157368003d30856d3bc (diff) |
nir: Fix load_const comparisons for CSE.
We want the size of a float per component, not the size of a whole vec4.
NIR instructions on i965:
total instructions in shared programs: 1261937 -> 1261929 (-0.00%)
instructions in affected programs: 114 -> 106 (-7.02%)
Looking at one of these examples (tesseract), it's from vec4 load_consts
for a MRT solid fill, which do get CSEed now that we don't memcmp off the
end of the const value and into the SSA def. For the 1-component loads
that are common in i965, we were only memcmping off into the rest of the
usually zero-filled const_value.
Reviewed-by: Connor Abbott <[email protected]>
Diffstat (limited to 'm4')
0 files changed, 0 insertions, 0 deletions