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authorJason Ekstrand <[email protected]>2018-02-28 19:57:44 -0800
committerJason Ekstrand <[email protected]>2018-03-01 15:11:01 -0800
commitff4726077d86800d33520581f154a27dac408588 (patch)
tree8306ac0ca888b6ea68b5df271170873a7036e0b2 /m4
parentf5305c1b44a81d8e022997e0f2f5bd7556be7dea (diff)
intel/fs: Set up sampler message headers in the visitor on gen7+
This gives the scheduler visibility into the headers which should improve scheduling. More importantly, however, it lets the scheduler know that the header gets written. As-is, the scheduler thinks that a texture instruction only reads it's payload and is unaware that it may write to the first register so it may reorder it with respect to a read from that register. This is causing issues in a couple of Dota 2 vertex shaders. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104923 Cc: [email protected] Reviewed-by: Francisco Jerez <[email protected]>
Diffstat (limited to 'm4')
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