diff options
| author | Kenneth Graunke <[email protected]> | 2017-07-31 22:04:25 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2017-08-02 10:01:34 -0700 |
| commit | 595a47b8293b1d97a3ae7dbfa8db703bfb4e7aae (patch) | |
| tree | 1bfa24c486478512fe7bf3aa491818d81c163f40 /m4/ax_pthread.m4 | |
| parent | 7cd50b9e47a8ad131795da270039da87e0175143 (diff) | |
i965: Delete pitch alignment assertion in get_blit_intratile_offset_el.
The cacheline alignment restriction is on the base address; the pitch
can be anything.
Fixes assertion failures when using primus (say, on glxgears, which
creates a 300x300 linear BGRX surface with a pitch of 1200):
intel_blit.c:190: get_blit_intratile_offset_el: Assertion `mt->surf.row_pitch % 64 == 0' failed.
Cc: [email protected]
Reviewed-by: Chris Wilson <[email protected]>
Diffstat (limited to 'm4/ax_pthread.m4')
0 files changed, 0 insertions, 0 deletions