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| author | Eric Anholt <[email protected]> | 2015-08-03 19:25:47 -0700 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2015-08-20 23:40:22 -0700 |
| commit | 0bba4fa070583f5fd8a0f7208fbfa181dc25e71b (patch) | |
| tree | 414a6907b45f2c8a6948c41f6a26bfc94903c1eb /m4/ax_gcc_func_attribute.m4 | |
| parent | ceb1a318424bf219eace29955ae473c1ccf9f8b8 (diff) | |
vc4: Allow QIR registers to be non-SSA.
Now that we have NIR, most of the optimization we still need to do is
peepholes on instruction selection rather than general dataflow
operations. This means we want to be able to have QIR be a lot closer to
the actual QPU instructions, just with virtual registers. Allowing
multiple instructions writing the same register opens up a lot of
possibilities.
Diffstat (limited to 'm4/ax_gcc_func_attribute.m4')
0 files changed, 0 insertions, 0 deletions