diff options
author | Kenneth Graunke <[email protected]> | 2013-03-01 15:23:53 -0800 |
---|---|---|
committer | Ian Romanick <[email protected]> | 2013-03-05 14:58:04 -0800 |
commit | 26e827b3099fe5c01dfb77bba48d0d6c5c334722 (patch) | |
tree | 11f8d8fceb6a7114b729571291198e5a65fc1b0d /include | |
parent | 44a5b5d161db496ec6a9c450a0f369b3356696f2 (diff) |
i965: Fix Crystal Well PCI IDs.
The second digit was off by one, which meant we accidentally treated
GTn as GT(n-1). This also meant no support for GT1 at all.
NOTE: This is a candidate for stable branches.
Signed-off-by: Kenneth Graunke <[email protected]>
(cherry picked from commit b88f74d63dca9db0f1b1cb9ce4d85f706c7a7fab)
Diffstat (limited to 'include')
-rw-r--r-- | include/pci_ids/i965_pci_ids.h | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 09dca5b0ed6..1e388f8cadd 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -53,12 +53,12 @@ CHIPSET(0x0A26, HASWELL_ULT_M_GT2_PLUS, hsw_gt2) CHIPSET(0x0A0A, HASWELL_ULT_S_GT1, hsw_gt1) CHIPSET(0x0A1A, HASWELL_ULT_S_GT2, hsw_gt2) CHIPSET(0x0A2A, HASWELL_ULT_S_GT2_PLUS, hsw_gt2) -CHIPSET(0x0D12, HASWELL_CRW_GT1, hsw_gt1) -CHIPSET(0x0D22, HASWELL_CRW_GT2, hsw_gt2) -CHIPSET(0x0D32, HASWELL_CRW_GT2_PLUS, hsw_gt2) -CHIPSET(0x0D16, HASWELL_CRW_M_GT1, hsw_gt1) -CHIPSET(0x0D26, HASWELL_CRW_M_GT2, hsw_gt2) -CHIPSET(0x0D36, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) -CHIPSET(0x0D1A, HASWELL_CRW_S_GT1, hsw_gt1) -CHIPSET(0x0D2A, HASWELL_CRW_S_GT2, hsw_gt2) -CHIPSET(0x0D3A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D02, HASWELL_CRW_GT1, hsw_gt1) +CHIPSET(0x0D12, HASWELL_CRW_GT2, hsw_gt2) +CHIPSET(0x0D22, HASWELL_CRW_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D06, HASWELL_CRW_M_GT1, hsw_gt1) +CHIPSET(0x0D16, HASWELL_CRW_M_GT2, hsw_gt2) +CHIPSET(0x0D26, HASWELL_CRW_M_GT2_PLUS, hsw_gt2) +CHIPSET(0x0D0A, HASWELL_CRW_S_GT1, hsw_gt1) +CHIPSET(0x0D1A, HASWELL_CRW_S_GT2, hsw_gt2) +CHIPSET(0x0D2A, HASWELL_CRW_S_GT2_PLUS, hsw_gt2) |