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authorDave Airlie <[email protected]>2017-11-06 02:03:43 +0000
committerDave Airlie <[email protected]>2017-11-13 07:17:09 +0000
commitbec716e8441e3fcef71ce8f9d17d98ddf5a652e0 (patch)
tree9885a1b6d4e3476ed47e334bc62f00b921b6f68d /include/pci_ids/radeonsi_pci_ids.h
parent031e591923fad7792a4e2e0522cf63a3ff62bc69 (diff)
radv: emit esgs ring size in one place.
This register is the same on all gpus so far, so emit it in one place and also for the pre-gfx9 gpus set the value in the pipeline creation. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
Diffstat (limited to 'include/pci_ids/radeonsi_pci_ids.h')
0 files changed, 0 insertions, 0 deletions