diff options
| author | Kristian Høgsberg <[email protected]> | 2014-09-22 04:44:19 -0700 |
|---|---|---|
| committer | Kristian Høgsberg <[email protected]> | 2014-12-08 16:33:59 -0800 |
| commit | cae7a2a0319e31eef0975edafc730efd3bd2c8d4 (patch) | |
| tree | 9d5a42ebbbf198a442c5062dc3010a5d386ce2dd /include/pci_ids/i965_pci_ids.h | |
| parent | 5bad948fa8a4fe812d254b6251e5e5dbd8a64e1c (diff) | |
i965/skl: Add Skylake PCI IDs
Signed-off-by: Kristian Høgsberg <[email protected]>
Diffstat (limited to 'include/pci_ids/i965_pci_ids.h')
| -rw-r--r-- | include/pci_ids/i965_pci_ids.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index 2e04301fbb4..3e3e8fe4083 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -109,6 +109,21 @@ CHIPSET(0x162A, bdw_gt3, "Intel(R) Iris Pro P6300 (Broadwell GT3e)") CHIPSET(0x162B, bdw_gt3, "Intel(R) Iris 6100 (Broadwell GT3)") CHIPSET(0x162D, bdw_gt3, "Intel(R) Broadwell GT3") CHIPSET(0x162E, bdw_gt3, "Intel(R) Broadwell GT3") +CHIPSET(0x1902, skl_gt1, "Intel(R) Skylake DT GT1") +CHIPSET(0x1906, skl_gt1, "Intel(R) Skylake ULT GT1") +CHIPSET(0x190A, skl_gt1, "Intel(R) Skylake SRV GT1") +CHIPSET(0x190B, skl_gt1, "Intel(R) Skylake Halo GT1") +CHIPSET(0x190E, skl_gt1, "Intel(R) Skylake ULX GT1") +CHIPSET(0x1912, skl_gt2, "Intel(R) Skylake DT GT2") +CHIPSET(0x1916, skl_gt2, "Intel(R) Skylake ULT GT2") +CHIPSET(0x191A, skl_gt2, "Intel(R) Skylake SRV GT2") +CHIPSET(0x191B, skl_gt2, "Intel(R) Skylake Halo GT2") +CHIPSET(0x191D, skl_gt2, "Intel(R) Skylake WKS GT2") +CHIPSET(0x191E, skl_gt2, "Intel(R) Skylake ULX GT2") +CHIPSET(0x1921, skl_gt2, "Intel(R) Skylake ULT GT2F") +CHIPSET(0x1926, skl_gt3, "Intel(R) Skylake ULT GT3") +CHIPSET(0x192A, skl_gt3, "Intel(R) Skylake SRV GT3") +CHIPSET(0x192B, skl_gt3, "Intel(R) Skylake Halo GT3") CHIPSET(0x22B0, chv, "Intel(R) Cherryview") CHIPSET(0x22B1, chv, "Intel(R) Cherryview") CHIPSET(0x22B2, chv, "Intel(R) Cherryview") |